DRV8412 Datasheet, PDF (5/28 Pages) Texas Instruments – Dual Full Bridge PWM Motor Driver

www.ti.com
Pin Functions
DRV8412
DRV8422
DRV8432
SLES242A – DECEMBER 2009 – REVISED DECEMBER 2009
NAME
AGND
BST_A
BST_B
BST_C
BST_D
GND
GND_A
GND_B
GND_C
GND_D
GVDD_A
GVDD_B
GVDD_C
GVDD_D
M1
M2
M3
NC
OC_ADJ
OTW
PIN
DRV8412
12
24
33
34
43
13
29
DRV8422
11
43
34
33
24
10
38
30
37
37
30
38
29
23
22
1
44
8
9
10
3,4,19,20,25,42
14
21
44
1
22
23
15
14
13
3,4,19,20,25,42
9
2
OUT_A
OUT_B
OUT_C
OUT_D
PVDD_A
PVDD_B
PVDD_C
PVDD_D
PWM_A
PWM_B
PWM_C
PWM_D
RESET_AB
RESET_CD
FAULT
28
31
36
39
26,27
32
35
40,41
17
15
7
5
16
6
18
39
36
31
28
40,41
35
32
26,27
6
8
16
18
7
17
5
VDD
2
21
VREG
11
12
(1) I = input, O = output, P = power
DRV8432
9
35
28
27
20
8
32
31
24
23
36
1
18
19
13
12
11
-
7
2
33
30
25
22
34
29
26
21
4
6
14
16
5
15
3
17
10
FUNCTION
(1)
DESCRIPTION
P
Analog ground
P
High side bootstrap supply (BST), external capacitor to OUT_A required
P
High side bootstrap supply (BST), external capacitor to OUT_B required
P
High side bootstrap supply (BST), external capacitor to OUT_C required
P
High side bootstrap supply (BST), external capacitor to OUT_D required
P
Ground
P
Power ground for half-bridge A requires close decoupling capacitor to
ground
P
Power ground for half-bridge B requires close decoupling capacitor to
ground
P
Power ground for half-bridge C requires close decoupling capacitor to
ground
P
Power ground for half-bridge D requires close decoupling capacitor to
ground
P
Gate-drive voltage supply
P
Gate-drive voltage supply
P
Gate-drive voltage supply
P
Gate-drive voltage supply
I
Mode selection pin
I
Mode selection pin
I
Reserved mode selection pin, AGND connection is recommended
-
No connection pin. Ground connection is recommended
O
Analog overcurrent programming pin, requires resistor to AGND
O
Overtemperature warning signal, open-drain, active-low. An internal
pull-up resistor to VREG (3.3 V) is provided on output. Level compliance
for 5-V logic can be obtained by adding external pull-up resistor to 5 V
O
Output, half-bridge A
O
Output, half-bridge B
O
Output, half-bridge C
O
Output, half-bridge D
P
Power supply input for half-bridge A requires close decoupling capacitor
to ground.
P
Power supply input for half-bridge B requires close decoupling capacitor
to gound.
P
Power supply input for half-bridge C requires close decoupling capacitor
to ground.
P
Power supply input for half-bridge D requires close decoupling capacitor
to ground.
I
Input signal for half-bridge A
I
Input signal for half-bridge B
I
Input signal for half-bridge C
I
Input signal for half-bridge D
I
Reset signal for half-bridge A and half-bridge B, active-low
I
Reset signal for half-bridge C and half-bridge D, active-low
O
Fault signal, open-drain, active-low. An internal pull-up resistor to VREG
(3.3 V) is provided on output. Level compliance for 5-V logic can be
obtained by adding external pull-up resistor to 5 V
P
Power supply for digital voltage regulator requires caacitor to ground for
decoupling.
P
Digital regulator supply filter pin requires 0.1-μF capacitor to AGND.
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Link(s): DRV8412 DRV8422 DRV8432