DRV8412 Datasheet, PDF (12/28 Pages) Texas Instruments – Dual Full Bridge PWM Motor Driver

DRV8412
DRV8422
DRV8432
SLES242A – DECEMBER 2009 – REVISED DECEMBER 2009
off the affected low side FET and keep the high side
FET at the same half brdige off until next PWM cycle;
when high side FET OC is detected, devcie will turn
off the affected high side FET and turn on the low
side FET at the half brdige until next PWM cycle.
In OC latching shut down mode, the CBC current limit
and error recovery circuitries are disabled and an
overcurrent condition will cause the device to
shutdown immediately. After shutdown, RESET_AB
and/or RESET_CD must be asserted to restore
normal operation after the overcurrent condition is
removed.
For added flexibility, the OC threshold is
programmable using a single external resistor
connected between the OC_ADJ pin and GND pin.
See Table 2 for information on the correlation
between programming-resistor value and the OC
threshold. It should be noted that a properly
functioning overcurrent detector assumes the
presence of a proper inductor or power ferrite bead at
the power-stage output. Short-circuit protection is not
guaranteed with direct short at the output pins of the
power stage.
Table 2. Programming-Resistor Values and OC
Threshold
OC-ADJUST RESISTOR
VALUES (kΩ)
22⁽¹⁾
MAXIMUM CURRENT BEFORE
OC OCCURS (A)
11.6
24
10.7
27
9.7
30
8.8
36
7.4
39
6.9
43
6.3
47
5.8
56
4.9
68
4.1
82
3.4
100
2.8
120
2.4
150
1.9
200
1.4
(1) Recommended to use in OC Latching Mode Only
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Overtemperature Protection
The DRV8412/22/32 have a two-level
temperature-protection system that asserts an
active-low warning signal (OTW) when the device
junction temperature exceeds 125°C (nominal) and, if
the device junction temperature exceeds 150°C
(nominal), the device is put into thermal shutdown,
resulting in all half-bridge outputs being set in the
high-impedance (Hi-Z) state and FAULT being
asserted low. OTSD is latched in this case and
RESET_AB and RESET_CD must be asserted low to
clear the latch.
Undervoltage Protection (UVP) and Power-On
Reset (POR)
The UVP and POR circuits of the DRV8412/22/32
fully protect the device in any power-up/down and
brownout situation. While powering up, the POR
circuit resets the overcurrent circuit and ensures that
all circuits are fully operational when the GVDD_X
and VDD supply voltages reach 9.8 V (typical).
Although GVDD_X and VDD are independently
monitored, a supply voltage drop below the UVP
threshold on any VDD or GVDD_X pin results in all
half-bridge outputs immediately being set in the
high-impedance (Hi-Z) state and FAULT being
asserted low. The device automatically resumes
operation when all supply voltage on the bootstrap
capacitors have increased above the UVP threshold.
DEVICE RESET
Two reset pins are provided for independent control
of half-bridges A/B and C/D. When RESET_AB is
asserted low, all four power-stage FETs in
half-bridges A and B are forced into a
high-impedance (Hi-Z) state. Likewise, asserting
RESET_CD low forces all four power-stage FETs in
half-bridges C and D into a high-impedance state. To
accommodate bootstrap charging prior to switching
start, asserting the reset inputs low enables weak
pulldown of the half-bridge outputs.
A rising-edge transition on reset input allows the
device to resume operation after a shut-down fault.
E.g., when either or both half-bridge A and B have
OC shutdown, a low to high transition of RESET_AB
pin will clear the fault and FAULT pin; when either or
both half-bridge C and D have OC shutdown, a low to
high transition of RESET_CD pin will clear the fault
and FAULT pin as well. When an OTSD or GVDD
undervoltage occurs, both RESET_AB and
RESET_CD need to have a low to high transition to
clear the fault and FAULT signal.
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