DRV8412 Datasheet, PDF (19/28 Pages) Texas Instruments – Dual Full Bridge PWM Motor Driver

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DRV8412
DRV8422
DRV8432
SLES242A – DECEMBER 2009 – REVISED DECEMBER 2009
Because an inductor usually saturates pretty quickly after reaching its current rating, it is recommended to use an
inductor with a doubled value or an inductor with a current rating well above the operating condition.
Parallel Mode Operation
For a device operated in parallel mode, a minimum of 30 nH to 100 nH inductance or a ferrite bead is required
after the output pins (e.g. OUT_A and OUT_B) before connecting the two channels together. This will help to
prevent any shoot through between two paralleled channels during switching transient due to mismatch of
paralleled channels (e.g., processor variation, unsymmetrical PCB layout, etc).
TEC Driver Application
For TEC driver or other non-motor related applications (e.g. resistive load or dc output), a low-pass LC filter can
be used to meet the requirement.
PCB LAYOUT RECOMMENDATION
PCB Material Recommendation
FR-4 Glass Epoxy material with 2 oz. copper on both top and bottom layer is recommended for improved thermal
performance (better heat sinking) and less noise susceptibility (lower PCB trace inductance).
Ground Plane
Because of the power level of these devices, it is recommended to use a big unbroken single ground plane for
the whole system / board. The ground plane can be easily made at bottom PCB layer. In order to minimize the
impedance and inductance of ground traces, the traces from ground pins should keep as short and wide as
possible before connected to bottom ground plane through vias. Multiple vias are suggested to reduce the
impedance of vias. Try to clear the space around the device as much as possible especially at bottom PCB side
to improve the heat spreading.
Decoupling Capacitor
High frequency decoupling capacitors (100 nF) on PVDD_X pins should be placed close to these pins and with a
short ground return path to minimize the inductance on the PCB trace.
AGND
AGND is a localized internal ground for logic signals. A 1-Ω resistor is recommended to be connected between
GND and AGND to isolate the noise from board ground to AGND. There are other two components are
connected to this local ground: 0.1-µF capacitor between VREG to AGND and Roc_adj resistor between
OC_ADJ and AGND. Capacitor for VREG should be placed close to VREG and AGND pin and connected
without vias.
Current Shunt Resistor
If current shunt resistor is connected between GND_X to GND or PVDD_X to PVDD, make sure there is only one
single path to connect each GND_X or PVDD_X pin to shunt resistor, and the path is short and symmetrical on
each sense path to minimize the measurement error due to additional resistance on the trace.
PCB LAYOUT EXAMPLE
An example of the schematic and PCB layout of DRV8412 are shown in Figure 14, Figure 15, and Figure 16.
Copyright © 2009, Texas Instruments Incorporated
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Product Folder Link(s): DRV8412 DRV8422 DRV8432