CD74HCT356 Datasheet, PDF (5/12 Pages) Texas Instruments – High-Speed CMOS Logic 8-Input Multiplexer/Register, Three-State

CD74HCT356
Absolute Maximum Ratings
DC Supply Voltage, V_CC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I_IK
For V_I < -0.5V or V_I > V_CC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I_OK
For V_O < -0.5V or V_O > V_CC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, I_O
For -0.5V < V_O < V_CC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
DC Output Source or Sink Current per Output Pin, I_O
For V_O > -0.5V or V_O < V_CC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC V_CC or Ground Current, I_CC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 2)
θ_JA (^oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
69
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
58
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150^oC
Maximum Storage Temperature Range . . . . . . . . . .-65^oC to 150^oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300^oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, T_A . . . . . . . . . . . . . . . . . . . . . . -55^oC to 125^oC
Supply Voltage Range, V_CC . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V_I, V_O . . . . . . . . . . . . . . . . . 0V to V_CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
25^oC
-40^oC TO 85^oC
PARAMETER
High Level Input
Voltage
SYMBOL V_I (V) I_O (mA) V_CC (V) MIN TYP MAX MIN
V_IH
-
-
4.5 to 2
-
-
2
5.5
MAX
-
Low Level Input
Voltage
V_IL
-
-
4.5 to -
- 0.8
-
0.8
5.5
High Level Output
Voltage
CMOS Loads
V_OH
V_IH or -0.02
4.5
4.4
-
-
4.4
-
V_IL
High Level Output
Voltage
TTL Loads
-4
4.5 3.98 -
-
3.84
-
Low Level Output
Voltage
CMOS Loads
V_OL
V_IH or 0.02
4.5
-
- 0.1
-
0.1
V_IL
Low Level Output
Voltage
TTL Loads
4
4.5
-
- 0.26
-
0.33
Input Leakage
Current
I_I
V_CC to
0
5.5
-
- ±0.1
-
±1
GND
Quiescent Device
Current
I_CC
V_CC or
0
5.5
-
-
8
-
80
GND
Additional Quiescent
∆I_CC
V_CC
-
4.5 to - 100 360
-
450
Device Current Per
(Note 3) -2.1
5.5
Input Pin: 1 Unit Load
3-State Leakage
Current
I_OZ
V_IL or V_O =
5.5
-
- ±0.5
-
±5
V_IH V_CC or
GND
NOTE:
3. For dual-supply systems theoretical worst case (V_I = 2.4V, V_CC = 5.5V) specification is 1.8mA.
-55^oC TO 125^oC
MIN MAX UNITS
2
-
V
-
0.8
V
4.4
-
V
3.7
-
V
-
0.1
V
-
0.4
V
-
±1
µA
-
160
µA
-
490
µA
-
±10
µA
5