CD74HCT356 Datasheet, PDF (1/12 Pages) Texas Instruments – High-Speed CMOS Logic 8-Input Multiplexer/Register, Three-State

Semiconductor
CD74HCT356
SCLS459A - June 2001 - Revised May 2003
High-Speed CMOS Logic
8-Input Multiplexer/Register, Three-State
Features
Description
• Edge-Triggered Data Flip-Flops
- Transparent Select Latches
• Buffered Inputs
• 3-State Complementary Outputs
• Bus Line Driving Capability
•
Typical Propagation
T_A = 25^oC
Delay:
V_CC
=
5V,
C_L
=
15pF,
- Clock to Output = 22ns
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• 4.5V to 5.5V Operation
• Direct LSTTL Input Logic Compatibility,
V_IL= 0.8V (Max), V_IH = 2V (Min)
• CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH
The CD74HCT356 consists of data selectors/multiplexers that
select one of eight sources. The data select bits (S0, S1, and
S2) are stored in transparent latches that are enabled by a low
latch enable input (LE).
The data is stored in edge-triggered flip-flops that are
triggered by a low-to-high clock transition.
In both types the 3-state outputs are controlled by three
output-enable inputs (OE1, OE2, and OE3).
Ordering Information
PART NUMBER
TEMP. RANGE
(^oC)
PACKAGE
CD74HCT356E
-55 to 125
20 Ld PDIP
CD74HCT356M96
-55 to 125
20 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.
Pinout
CD74HCT356
(PDIP or SOIC)
TOP VIEW
D7 1
D6 2
D5 3
D4 4
D3 5
D2 6
D1 7
D0 8
CP 9
GND 10
20 V_CC
19 Y
18 Y
17 OE3
16 OE2
15 OE1
14 S0
13 S1
12 S2
11 LE
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1