BQ24750_07 Datasheet, PDF (5/38 Pages) Texas Instruments – Host-controlled Multi-chemistry Battery Charger with Integrated System Power Selector and AC Over-Power Protection

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bq24750
SLUS735 – DECEMBER 2006
Table 1. TERMINAL FUNCTIONS – 28-PIN QFN (continued)
TERMINAL
DESCRIPTION
NAME
NO.
SRN
Charge current sense resistor, negative input. An optional 0.1-µF ceramic capacitor is placed from SRN pin to AGND
18 for common-mode filtering. An optional 0.1-µF ceramic capacitor is placed from SRN to SRP to provide
differential-mode filtering.
SRP
19 Charge current sense resistor, positive input. (See comments for SRN.)
CELLS
20 2, 3 or 4 cells selection logic input. Logic low programs 3 cell. Logic high programs 4 cell. Floating programs 2 cell.
DPMDET
Dynamic power management (DPM) input current loop active, open-drain output status. Logic low indicates input
21 current is being limited by reducing the charge current. Connect 10-kΩ pullup resistor from DPMDET to VREF or a
different pullup-supply rail. Time delay is 8 ms.
PGND
22
Power ground. On PCB layout, connect directly to source of low-side power MOSFET, to ground connection of input
and output capacitors of the charger. Only connect to AGND through the power pad underneath the IC.
LODRV
23 PWM low side driver output. Connect to the gate of the low-side power MOSFET with a short trace.
REGN
24
PWM low side driver positive 6-V supply output. Connect a 1-µF ceramic capacitor from REGN to PGND, close to the
IC. Use for high-side driver bootstrap voltage by connecting a small-signal Schottky diode from REGN to BTST.
PWM high side driver negative supply. Connect to the phase switching node (junction of the low-side power MOSFET
PH
25 drain, high-side power MOSFET source, and output inductor). Connect the 0.1-µF bootstrap capacitor from from PH to
BTST.
HIDRV
26 PWM high side driver output. Connect to the gate of the high-side power MOSFET with a short trace.
BTST
27
PWM high side driver positive supply. Connect a 0.1-µF bootstrap ceramic capacitor from BTST to PH. Connect a
small bootstrap Schottky diode from REGN to BTST.
PVCC
IC power positive supply. Connect to the common-source (diode-OR) point: source of high-side P-channel MOSFET
28 and source of reverse-blocking power P-channel MOSFET. Place a 1-µF ceramic capacitor from PVCC to PGND pin
close to the IC.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾
Voltage range
Maximum difference voltage
Junction temperature range
Storage temperature range
PVCC, ACP, ACN, SRP, SRN, BAT, BATDRV, ACDRV
PH
REGN, LODRV, VADJ, ACSET, SRSET, TS, ACDET, ACOP, CHGEN, CELLS,
ACGOOD
VDAC
VREF, IADAPT
BTST, HIDRV with respect to AGND and PGND
ACP–ACN, SRP–SRN, AGND–PGND
VALUE
–0.3 to 30
–1 to 30
–0.3 to 7
–0.3 to 5.5
–0.3 to 3.6
–0.3 to 36
–0.5 V to 0.5
–40 to 155
–55 to 155
UNIT
V
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
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