BQ24750_07 Datasheet, PDF (20/38 Pages) Texas Instruments – Host-controlled Multi-chemistry Battery Charger with Integrated System Power Selector and AC Over-Power Protection

bq24750
SLUS735 – DECEMBER 2006
www.ti.com
When the adapter is not detected, the ACDRV output is pulled to PVCC to turn off the ACFET, disconnecting the
adapter from system. BATDRV stays at ACN – 6 V to connect the battery to system.
At 700 ms after adapter is detected, the system begins to switch from the battery to the adapter. The PVCC
voltage must be 250 mV above BAT to enable the switching. The break-before-make logic turns off both ACFET
and BATFET for 10µs before ACFET turns on. This isolates the battery from shoot-through current or any large
discharging current. The BATDRV output is pulled up to ACN and the ACDRV pin is set to ACN – 6 V by an
internal regulator to turn on the p-channel ACFET, connecting the adapter to the system.
When the adapter is removed, the system waits till PVCC drops back to within 250 mV above BAT to switch
from the adapter back to the battery. The break-before-make logic ensures a 10-µs dead time. The ACDRV
output is pulled up to PVCC and the BATDRV pin is set to ACN – 6 V by an internal regulator to turn on the
p-channel BATFET, connecting the battery to the system.
Asymmetrical gate drive for the ACDRV and BATDRV drivers provides fast turn-off and slow turn-on of the
ACFET and BATFET to help the break-before-make logic and to allow a soft-start at turn-on of either FET. The
soft-start time can be further increased, by putting a capacitor from gate to source of the p-channel power
MOSFETs.
Automatic Internal Soft-Start Charger Current
The charger automatically soft-starts the charger regulation current every time the charger is enabled to ensure
there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists of
stepping-up the charger regulation current into 8 evenly divided steps up to the programmed charge current.
Each step lasts approximately 1 ms, for a typical rise time of 8 ms. No external components are needed for this
function.
Converter Operation
The synchronous-buck PWM converter uses a fixed-frequency (300 kHz) voltage mode with a feed-forward
control scheme. A Type-III compensation network allows the use of ceramic capacitors at the output of the
converter. The compensation input stage is internally connected between the feedback output (FBO) and the
error-amplifier input (EAI). The feedback compensation stage is connected between the error amplifier input
(EAI) and error amplifier output (EAO). The LC output filter is selected for a nominal resonant frequency of 8
kHz–12.5 kHz.
The
resonant
frequency,
f_o, is given by:
f_o
+
2p
1
Ǹ_LoCo
where
(from Figure
1 schematic)
• C_O = C11 + C12
• L_O = L1
An internal sawtooth ramp is compared to the internal EAO error-control signal to vary the duty cycle of the
converter. The ramp height is one-fifteenth of the input adapter voltage, making it always directly proportional to
the input adapter voltage. This cancels out any loop-gain variation due to a change in input voltage, and
simplifies the loop compensation. The ramp is offset by 300 mV in order to allow a 0% duty cycle when the EAO
signal is below the ramp. The EAO signal is also allowed to exceed the sawtooth ramp signal in order to operate
with a 100% duty-cycle PWM request. Internal gate-drive logic allows a 99.98% duty-cycle while ensuring that
the N-channel upper device always has enough voltage to stay fully on. If the BTST-to-PH voltage falls below 4
V for more than 3 cycles, the high-side N-channel power MOSFET is turned off and the low-side N-channel
power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the high-side
driver returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected falling low again due to
leakage current discharging the BTST capacitor below 4 V, and the reset pulse is reissued.
The 300-kHz fixed-frequency oscillator tightly controls the switching frequency under all conditions of input
voltage, battery voltage, charge current, and temperature. This simplifies output-filter design, and keeps it out of
the audible noise region. The charge-current sense resistor R_SR should be designed with at least half or more of
the total output capacitance placed before the sense resistor, contacting both sense resistor and the output
inductor; and the other half, or remaining capacitance placed after the sense resistor. The output capacitance
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