BQ24750_07 Datasheet, PDF (10/38 Pages) Texas Instruments – Host-controlled Multi-chemistry Battery Charger with Integrated System Power Selector and AC Over-Power Protection

bq24750
SLUS735 – DECEMBER 2006
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
7.0 V ≤ V_PVCC≤ 24 V, 0°C < T_J < +125°C, typical values are at T_A = 25°C, with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
PWM OSCILLATOR
F_SW
PWM switching frequency
V_{RAMP_HEIGHT}
PWM ramp height
QUIESCENT CURRENT
As percentage of PVCC
240
6.6
360 kHz
%PVCC
I_{OFF_STATE}
Total off-state battery current from
SRP, SRN, BAT, VCC, BTST, PH,
etc.
V_BAT = 16.8 V, V_ACDET < 0.6 V,
V_PVCC > 5 V, T_J = 0 to 85°C
7
10
µA
I_{BAT_ON}
I_{BAT_LOAD_CD}
I_{BAT_LOAD_CE}
I_AC
I_{AC_SWITCH}
Battery on-state quiescent current
Internal battery load current, charge
disbled
Internal battery load current, charge
enabled
Adapter quiescent current
Adapter switching quiescent current
V_BAT = 16.8 V, 0.6V < V_ACDET < 2.4 V,
V_PVCC > 5V
Charge is disabled:
V_BAT = 16.8 V, V_ACDET > 2.4 V,
V_PVCC > 5 V
Charge is enabled:
V_BAT = 16.8 V, V_ACDET > 2.4 V,
V_PVCC > 5 V
V_PVCC = 20 V, charge disabled
V_PVCC = 20 V, charge enabled, converter
running, total gate charge = 2 × 10 nC
1
mA
3
5 mA
6 10
12 mA
2.8
4 mA
25
mA
INTERNAL SOFT START (8 steps to regulation current)
Soft start steps
8
step
Soft start step time
1.7
ms
CHARGER SECTION POWER-UP SEQUENCING
Charge-enable delay after power-up Delay from when adapter is detected to
when the charger is allowed to turn on
518 700
908
ms
LOGIC INPUT PIN CHARACTERISTICS (CHGEN)
V_{IN_LO}
Input low threshold voltage
V_{IN_HI}
Input high threshold voltage
I_BIAS
Input bias current
LOGIC INPUT PIN CHARACTERISTICS (CELLS)
V_CHGEN = 0 to V_REGN
0.8
V
2.1
1
µA
V_{IN_LO}
V_{IN_MID}
Input low threshold voltage, 3 cells
Input mid threshold voltage, 2 cells
CELLS voltage falling edge
CELLS voltage rising for MIN,
CELLS voltage falling for MAX
0.5
0.8
1.8
V
V_{IN_HI}
I_{BIAS_FLOAT}
Input high threshold voltage, 4 cells
Input bias float current for 2-cell
selection
CELLS voltage rising
V_CHGEN = 0 to V_REGN
2.5
–1
1
µA
OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS (ACGOOD)
V_{OUT_LO}
Output low saturation voltage
Delay, ACGOOD falling
Sink Current = 4 mA
0.5
V
518 700
908
ms
Delay, ACGOOD rising
10
µs
OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS (DPMDET)
V_{OUT_LO}
Output low saturation voltage
Delay, DPMDET rising/falling
Sink Current = 5 mA
0.5
V
10
ms
10
Submit Documentation Feedback