BQ24750_07 Datasheet, PDF (4/38 Pages) Texas Instruments – Host-controlled Multi-chemistry Battery Charger with Integrated System Power Selector and AC Over-Power Protection

bq24750
SLUS735 – DECEMBER 2006
www.ti.com
Table 1. TERMINAL FUNCTIONS – 28-PIN QFN
TERMINAL
DESCRIPTION
NAME
NO.
CHGEN
1 Charge enable active-low logic input. LO enables charge. HI disables charge.
ACN
Adapter current sense resistor, negative input. An optional 0.1-µF ceramic capacitor is placed from ACN pin to AGND
2 for common-mode filtering. An optional 0.1-µF ceramic capacitor is placed from ACN to ACP to provide
differential-mode filtering.
ACP
3 Adapter current sense resistor, positive input. (See comments with ACN description)
ACDRV
AC adapter to system-switch driver output. Connect directly to the gate of the ACFET P-channel power MOSFET and
the reverse conduction blocking P-channel power MOSFET. Connect both FETs as common-source. Connect the
ACFET drain to the system-load side. The PVCC should be connected to the common-source node to ensure that the
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driver logic is always active when needed. If needed, an optional capacitor from gate to source of the ACFET is used
to slow down the ON and OFF times. The internal gate drive is asymmetrical, allowing a quick turn-off and slower
turn-on in addition to the internal break-before-make logic with respect to the BATDRV. The output goes into linear
regulation mode when the input sensed current exceeds the ACOC threshold. ACDRV is latched off after ACOP
voltage exceeds 2 V, to protect the charging system from an ACFET-overpower condition.
ACDET
Adapter detected voltage set input. Program the adapter detect threshold by connecting a resistor divider from
5
adapter input to ACDET pin to AGND pin. Adapter voltage is detected if ACDET-pin voltage is greater than 2.4 V. The
I_ADAPT current sense amplifier is active when the ACDET pin voltage is greater than 0.6 V. Input overvoltage, ACOV,
disables charge and ACDRV when ACDET > 3.1 V. ACOV does not latch
ACSET
Adapter current set input. The voltage ratio of ACSET voltage versus VDAC voltage programs the input current
6
regulation set-point during Dynamic Power Management (DPM). Program by connecting a resistor divider from VDAC
to ACSET to AGND; or by connecting the output of an external DAC to the ACSET pin and connect the DAC supply
to the VDAC pin.
ACOP
Input power limit set input. Program the input over-power time constant by placing a ceramic capacitor from ACOP to
7
AGND. The capacitor sets the time that the input current limit, ACOC, can be sustained before exceeding the
power-MOSFET power limit. When the ACOP voltage exceeds 2 V, then the ACDRV latches off to protect the charge
system from an over-power condition, ACOP. Reset latch by toggling ACDET or PVCC_UVLO.
TS
8
Temperature qualification voltage input for battery pack negative temperature coefficient thermistor. Program the hot
and cold temperature window with a resistor divider from VREF to TS to AGND.
AGND
9
Analog ground. On PCB layout, connect to the analog ground plane, and only connect to PGND through the power
pad underneath the IC.
VREF
10
3.3-V regulated voltage output. Place a 1-µF ceramic capacitor from VREF to AGND pin close to the IC. This voltage
could be used for ratiometric programming of voltage and current regulation.
VDAC
Charge voltage set reference input. Connect the VREF or external DAC voltage source to the VDAC pin. Battery
voltage, charge current, and input current are programmed as a ratio of the VDAC pin voltage versus the VADJ,
11 SRSET, and ACSET pin voltages, respectively. Place resistor dividers from VDAC to VADJ, SRSET, and ACSET pins
to AGND for programming. A DAC could be used by connecting the DAC supply to VDAC and connecting the output
to VADJ, SRSET, or ACSET.
VADJ
Charge voltage set input. The voltage ratio of VADJ voltage versus VDAC voltage programs the battery voltage
12
regulation set-point. Program by connecting a resistor divider from VDAC to VADJ, to AGND; or, by connecting the
output of an external DAC to VADJ, and connect the DAC supply to VDAC. VADJ connected to REGN programs the
default of 4.2 V per cell.
ACGOOD
13
Valid adapter active-low detect logic open-drain output. Pulled low when Input voltage is above programmed ACDET.
Connect a 10-kΩ pullup resistor from ACGOOD to VREF, or to a different pullup-supply rail.
BATDRV
Battery to system switch driver output. Gate drive for the battery to system load BAT PMOS power FET to isolate the
system from the battery to prevent current flow from the system to the battery, while allowing a low impedance path
from battery to system and while discharging the battery pack to the system load. Connect this pin directly to the gate
14 of the input BAT P-channel power MOSFET. Connect the source of the FET to the system load voltage node.
Connect the drain of the FET to the battery pack positive node. An optional capacitor is placed from the gate to the
source to slow-down the switching times. The internal gate drive is asymmetrical to allow a quick turn-off and slower
turn-on, in addition to the internal break-before-make logic with respect to the ACDRV.
IADAPT
15
Adapter current sense amplifier output. IADAPT voltage is 20 times the differential voltage across ACP-ACN. Place a
100-pF or less ceramic decoupling capacitor from IADAPT to AGND.
SRSET
Charge current set input. The voltage ratio of SRSET voltage versus VDAC voltage programs the charge current
16 regulation set-point. Program by connecting a resistor divider from VDAC to SRSET to AGND; or by connecting the
output of an external DAC to SRSET pin and connect the DAC supply to VDAC pin.
Battery voltage remote sense. Directly connect a kelvin sense trace from the battery pack positive terminal to the BAT
BAT
17 pin to accurately sense the battery pack voltage. Place a 0.1-µF capacitor from BAT to AGND close to the IC to filter
high-frequency noise.
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