BQ24150A Datasheet, PDF (5/41 Pages) Texas Instruments – Fully Integrated Switch-Mode One-Cell Li-Ion Charger With Full USB Compliance and USB-OTG Support

bq24150A
bq24151A
www.ti.com ..................................................................................................................................................................................................... SLUS931 – APRIL 2009
ELECTRICAL CHARACTERISTICS (continued)
Circuit of Figure 1, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (charger mode operation), T_J = 0°C to 125°C, T_J = 25°C for
typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
INPUT CURRENT LIMITING
I_IN
Input current limiting threshold
VREF BIAS REGULATOR
USB charge
mode
I_IN = 100 mA
I_IN = 500 mA
V_REF
Internal bias regulator voltage
V_REF output short current limit
BATTERY RECHARGE THRESHOLD
VBUS >V_IN(min) or V_(AUXPWR) > V_(BAT)min,
I_(VREF) = 1 mA, C_(VREF) = 1 µF
V_(RCH)
Recharge threshold voltage
Deglitch time
STAT OUTPUTS
Below V_(OREG)
V_(AUXPWR) decreasing below threshold,
t_FALL = 100 ns, 10-mV overdrive
V_OL(STAT)
Low-level output saturation voltage, STAT
High-level leakage current for STAT
I_O = 10 mA, sink current
Voltage on STAT pin is 5 V
I²C BUS LOGIC LEVELS AND TIMING CHARACTERISTICS
V_OL
Output low threshold level
V_IL
Input low threshold level
V_IH
Input high threshold level
I_(BIAS)
Input bias current
f_(SCL)
SCL clock frequency
BATTERY DETECTION
I_O = 10 mA, sink current
V_(pull-up) = 1.8 V, SDA and SCL
I_(DETECT)
Battery detection current before charge done
(sink current) ⁽¹⁾
Battery detection time
Begins after termination detected,
V_(AUXPWR) ≤ V_(OREG)
SLEEP COMPARATOR
V_(SLP)
Sleep-mode entry threshold,
V_BUS - V_AUXPWR
Sleep-mode exit hysteresis
V_{(SLP_EXIT)}
Deglitch time for VBUS rising above V_(SLP) +
V_{(SLP_EXIT)}
UNDERVOLTAGE LOCKOUT
2.3 V ≤ V_(AUXPWR) ≤ V_(OREG), V_BUS falling
2.3 V ≤ V_(AUXPWR) ≤ V_(OREG)
Rising voltage, 2-mV overdrive, t_RISE = 100 ns
UVLO
IC active threshold voltage
VBUS rising
UVLO_(HYS)
PWM
IC active hysteresis
VBUS falling from above UVLO
Voltage from BOOT pin to SW pin
During charge or boost operation
Internal top reverse blocking MOSFET
on-resistance
I_IN(LIMIT) = 500 mA, Measured from VBUS to PMID
Internal top N-channel Switching MOSFET
on-resistance
Measured from PMID to SW, V_BOOT - V_SW= 4V
Internal bottom N-channel MOSFET
on-resistance
Measured from SW to PGND
f_(OSC)
Oscillator frequency
Frequency accuracy
D_(MAX)
D_(MIN)
Maximum duty cycle
Minimum duty cycle
Synchronous mode to non-synchronous mode
transition current threshold⁽²⁾
Low side MOSFET cycle by cycle current sensing
MIN TYP MAX UNIT
88
93
98 mA
450
475
500
2
6.5
V
30
mA
100
120
150 mV
130
ms
0.4
V
1 µA
0.4
V
0.4
V
1.2
V
1 µA
3.4 MHz
–0.45
mA
262
ms
0
40
100 mV
40
100
160 mV
30
ms
3.05
3.3 3.55
V
120
150
mV
6.5
V
180
250
120
250 mΩ
110
–10%
0
3
99.5%
100
200
10%
MHz
mA
(1) Negative charge current means the charge current flows from the battery to charger (discharging battery).
(2) Bottom N-channel MOSFET always turns on for ≈60 ns and then turns off if current is too low.
Copyright © 2009, Texas Instruments Incorporated
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