BQ24150A Datasheet, PDF (23/41 Pages) Texas Instruments – Fully Integrated Switch-Mode One-Cell Li-Ion Charger With Full USB Compliance and USB-OTG Support

bq24150A
bq24151A
www.ti.com ..................................................................................................................................................................................................... SLUS931 – APRIL 2009
ANY STATE
VBUS<VUVLO
VAUXPWR<VSHORT
POWER DOWN
VBUS>VUVLO
VAUXPWR<VLOWV
(bq24150A)
VAUXPWR>VSHORT
VBUS<V_UVLO
HZ_MODE=1
or VBUS<VUVLO, VAUXPWR>VSHORT
HIGH
IMPEDANCE
VBUS>VUVLO
HZ_MODE=0, OPA_MODE=0
CHARGE
CONFIGURE
OPA_MODE=1
HZ_MODE=0
VAUXPWR>VLOWV
HZ_MODE=1
Or
VAUXPWR<VLOWV
HZ_MODE=1
HZ_MODE=1
or
VAUXPWR<VBATMIN
BOOST
CONFIGURE
OPA_MODE=1
HZ_MODE=0
START UP
No FAULTS
BOOST
OPA_MODE=0
or FAULTS
OPA_MODE=1
HZ_MODE=0
OPA_MODE=0
VAUXPWR<VSHORT
or VBUS<VBUS(MIN)
or FAULTS
V_AUXPWR<V_SHORT
V_BUS>V_BUS(MIN)
NO FAULTS
VAUXPWR>VSHORT
or VBUS<VBUS(MIN)
or FAULTS
SHORT
CIRCUIT
PWM CHARGE
VAUXPWR>VSHORT, VBUS>VBUS(MIN)
NO FAULTS
Figure 26. State Diagram for bq24150A/1A
SERIAL INTERFACE DESCRIPTION
I²C™ is a 2-wire serial interface developed by Philips Semiconductor (see I²C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the
bus is idle, both SDA and SCL lines are pulled high. All the I²C compatible devices connect to the I²C bus
through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal
processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The
master also generates specific conditions that indicate the START and STOP of data transfer. A slave device
receives and/or transmits data on the bus under control of the master device.
The bq24150A/1A device works as a slave and supports the following data transfer modes, as defined in the
I²C-Bus™ Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (up to 3.4 Mbps
in write mode). The interface adds flexibility to the battery charge solution, enabling most functions to be
programmed to new values depending on the instantaneous application requirements. Register contents remain
intact as long as supply voltage remains above 2.2 V (typical). I²C is asynchronous, which means that it runs off
of SCL. The device has no noise or glitch filtering on SCL, so SCL input needs to be clean. Therefore, it is
recommended that SDA changes while SCL is LOW.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to
as the HS-mode. The bq24150A/1A device only supports 7-bit addressing. The device 7-bit address is defined as
‘1101011’ (6BH).
F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 27. All I²C-compatible devices should
recognize a start condition.
Copyright © 2009, Texas Instruments Incorporated
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