BQ24150A Datasheet, PDF (2/41 Pages) Texas Instruments – Fully Integrated Switch-Mode One-Cell Li-Ion Charger With Full USB Compliance and USB-OTG Support

bq24150A
bq24151A
SLUS931 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION CONTINUED
During the charging process, the bq24150A/1A monitors its junction temperature (T_J) and reduces the charge
current once T_J increases to approximately 125°C. To support USB OTG device, bq24150A/1A provides VBUS
(approximately 5.05 V) by boosting the battery voltage. The bq24150A/1A is available in 20-pin WCSP package.
WCSP PACKAGE
(Top View)
A1
A2
A3
A4
VBUS
VBUS
BOOT
SCL
B1
PMID
B2
PMID
C1
C2
SW
SW
B3
PMID
C3
SW
B4
SDA
C4
STAT
D1
PGND
E1
CSIN
D2
PGND
D3
PGND
D4
OTG
E2
E3
E4
AUX
PWR
VREF ^CSOUT
NAME
CSOUT
VBUS
PMID
SW
BOOT
PGND
CSIN
SCL
SDA
STAT
TERMINAL
NO.
E4
A1, A2
B1, B2, B3
C1, C2, C3
A3
D1, D2, D3
E1
A4
B4
C4
VREF
E3
AUXPWR
E2
OTG
D4
TERMINAL FUNCTIONS
I/O
DESCRIPTION
I
Battery voltage and current sense input. Bypass it with a ceramic capacitor (minimum 0.1 µF) to
PGND if there are long inductive leads to battery.
I
Charger input voltage. Bypass it with a 1-µF ceramic capacitor from VBUS to PGND.
O
Connection point between reverse blocking MOSFET and high-side switching MOSFET. Bypass it
with a minimum of 3.3-µF capacitor from PMID to PGND.
O
Internal switch to output inductor connection.
O
Boot-strapped capacitor for the high-side MOSFET gate driver. Connect a 10-nF ceramic capacitor
(voltage rating above 10 V) from BOOT pin to SW pin.
Power ground
I
Charge current-sense input. Battery current is sensed via the voltage drop across an external sense
resistor. A 0.1-µF ceramic capacitor to PGND is required.
I
I²C interface clock. Open drain output, connect a 10-kΩ pullup resistor to 1.8V rail
I/O
I²C interface data. Open drain output, connect a 10-kΩ pullup resistor to 1.8V rail
Charge status pin. Pull low when charge in progress. Open drain for other conditions. During faults, a
O
128-µS pulse is sent out. STAT pin can be disabled by the EN_STAT bit in control register. STAT can
be used to drive a LED or communicate with a host processor.
O
Internal bias regulator voltage. Connect a 1-µF ceramic capacitor from this output to PGND. External
load on VREF is not allowed.
I
Auxiliary power supply, connected to the battery pack to provide power in high-impedance mode.
Bypass it with a 1-µF ceramic capacitor from this pin to PGND.
Boost mode enable control or input current limiting selection pin. When OTG is in active status,
bq24150A/1A is forced to operate in boost mode. It has higher priority over I²C control and can be
I
disabled through control register. The logic voltage level at OTG active status can also be controlled.
At POR, the OTG pin is default to be used as the input current limiting selection pin. When OTG =
High, Iin – limit = 500mA and when OTG = Low, Iin – limit = 100mA, see the Control Register for
details.
2
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