74HC138D-T Datasheet, PDF (5/19 Pages) Texas Instruments – High-Speed CMOS Logic 3- to 8-Line Decoder/Demultiplexer Inverting and Noninverting

CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238
Switching Specifications Input t_r, t_f = 6ns (Continued)
PARAMETER
Enable to Output
HC/HCT138
TEST
25^oC
SYMBOL CONDITIONS V_CC (V) MIN TYP MAX
t_PLH, t_PHL C_L = 50pF
2
-
- 150
4.5
-
-
30
-40^oC TO
85^oC
-55^oC TO 125^oC
MIN MAX MIN MAX UNITS
-
190
-
265 ns
-
38
-
53
ns
6
-
-
26
-
33
-
45
ns
Output Transition Time
(Figure 1)
t_TLH, t_THL C_L = 50pF
2
-
-
75
-
95
-
110 ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Power Dissipation
Capacitance (Notes 3, 4)
C_PD C_L = 15pF
5
-
67
-
-
-
-
-
pF
Input Capacitance
HCT TYPES
Propagation Delay
Address to Output
Enable to Output
HC/HCT138
C_IN
-
-
-
-
10
-
10
-
10
pF
t_PLH, t_PHL C_L = 50pF
C_L = 15pF
t_PLH, t_PHL C_L = 50pF
4.5
-
-
35
-
44
-
5
-
14
-
-
-
-
4.5
-
-
35
-
44
-
53
ns
-
ns
53
ns
Enable to Output
HC/HCT238
t_PLH, t_PHL C_L = 15pF
4.5
-
-
40
-
50
-
60
ns
Output Transition Time
(Figure 2)
t_TLH, t_THL C_L = 50pF
4.5
-
-
15
-
19
-
22
ns
Power Dissipation
Capacitance (Notes 3, 4)
C_PD C_L = 15pF
5
-
67
-
-
-
-
-
pF
Input Capacitance
C_IN
-
-
-
-
10
-
10
-
NOTES:
3. C_PD is used to determine the dynamic power consumption, per gate.
4. P_D = V_CC2 f_i (C_PD + C_L) where f_i = Input Frequency, C_L = Output Load Capacitance, V_CC = Supply Voltage.
10
pF
Test Circuits and Waveforms
t_r = 6ns
INPUT
90%
50%
10%
t_f = 6ns
V_CC
GND
t_THL
INVERTING
OUTPUT
t_PHL
t_TLH
90%
50%
10%
t_PLH
FIGURE 7. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
t_r = 6ns
INPUT
2.7V
1.3V
0.3V
t_f = 6ns
3V
GND
t_THL
INVERTING
OUTPUT
t_PHL
t_TLH
90%
1.3V
10%
t_PLH
FIGURE 8. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5