74HC138D-T Datasheet, PDF (1/19 Pages) Texas Instruments – High-Speed CMOS Logic 3- to 8-Line Decoder/Demultiplexer Inverting and Noninverting

Data sheet acquired from Harris Semiconductor
SCHS147I
October 1997 - Revised August 2004
CD54/74HC138, CD54/74HCT138,
CD54/74HC238, CD54/74HCT238
High-Speed CMOS Logic 3- to 8-Line Decoder/
Demultiplexer Inverting and Noninverting
[ /Title
(CD74
HC138
,
CD74
HCT13
8,
CD74
HC238
,
CD74
HCT23
8)
/Sub-
ject
(High
Speed
Features
• Select One Of Eight Data Outputs
Active Low for 138, Active High for 238
• l/O Port or Memory Selector
• Three Enable Inputs to Simplify Cascading
•
Typical
C_L = 15
Propagation Delay
pF, T_A = 25^oC
of
13
ns
at
V_CC
=
5
V,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
Ordering Information
PART NUMBER
CD54HC138F3A
CD54HC238F3A
CD54HCT138F3A
CD54HCT238F3A
CD74HC138E
CD74HC138M
CD74HC138MT
CD74HC138M96
CD74HC238E
TEMP. RANGE
(^oC)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
• HC Types
- 2 V to 6 V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC
at V_CC = 5 V
• HCT Types
- 4.5-V to 5.5-V Operation
- Direct LSTTL Input Logic Compatibility,
V_IL= 0.8 V (Max), V_IH = 2 V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH
CD74HC238M
CD74HC238MT
CD74HC238M96
CD74HC238NSR
CD74HC238PW
CD74HC238PWR
CD74HC238PWT
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld TSSOP
Description
CD74HCT138E
-55 to 125
16 Ld PDIP
The ’HC138, ’HC238, ’HCT138, and ’HCT238 are high-speed
silicon-gate CMOS decoders well suited to memory address
decoding or data-routing applications. Both circuits feature
low power consumption usually associated with CMOS
circuitry, yet have speeds comparable to low-power Schottky
TTL logic. Both circuits have three binary select inputs (A0,
A1, and A2). If the device is enabled, these inputs determine
which one of the eight normally high outputs of the
HC/HCT138 series go low or which of the normally low
outputs of the HC/HCT238 series go high.
Two active low and one active high enables (E1, E2, and E3)
are provided to ease the cascading of decoders. The
decoder’s eight outputs can drive ten low-power Schottky
TTL equivalent loads.
CD74HCT138M
-55 to 125
16 Ld SOIC
CD74HCT138MT
-55 to 125
16 Ld SOIC
CD74HCT138M96
-55 to 125
16 Ld SOIC
CD74HCT238E
-55 to 125
16 Ld PDIP
CD74HCT238M
-55 to 125
16 Ld SOIC
CD74HCT238M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2004, Texas Instruments Incorporated
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