ADS6245 Datasheet, PDF (47/76 Pages) Texas Instruments – DUAL CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS

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ADS6245, ADS6244
ADS6243, ADS6242
SLAS542A – MAY 2007 – REVISED JULY 2007
So, the fine gain can be used to trade-off between SFDR and SNR. The coarse gain makes it possible to get
best SFDR but without losing SNR significantly. At high input frequencies, the gains are especially useful as the
SFDR improvement is significant with marginal degradation in SINAD.
The gains can be programmed using the register bits <COARSE GAIN> (Table 19) and <FINE GAIN>
(Table 18). Note that the default gain after reset is 0 dB.
GAIN, dB
0
3.5
1
2
3
4
5
6
Table 22. Full-Scale Range Across Gains
TYPE
Default (after reset)
Coarse setting (fixed)
Fine setting (programmable)
FULL-SCALE, V_pp
2
1.34
1.78
1.59
1.42
1.26
1.12
1.00
CLOCK INPUT
The ADS624X clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS),
with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to
VCM using internal 5-kΩ resistors as shown in Figure 89. This allows using transformer-coupled drive circuits for
sine wave clock or ac-coupling for LVPECL, LVDS clock sources (see Figure 91 and Figure 93). Figure 90
shows the impedance looking into the clock input pins of the device.
Copyright © 2007, Texas Instruments Incorporated
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