ADS6245 Datasheet, PDF (20/76 Pages) Texas Instruments – DUAL CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS

ADS6245, ADS6244
ADS6243, ADS6242
SLAS542A – MAY 2007 – REVISED JULY 2007
www.ti.com
Table 17. Serial Register D
REGISTER
ADDRESS
BITS
A4 - A0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0B
<CUSTOM A>
CUSTOM PATTERN (LOWER 11 BITS)
D10 - D0
<CUSTOM A> Lower 11 bits of custom pattern <DATAOUT10>…<DATAOUT0>
Table 18. Serial Register E
REGISTER
ADDRESS
A4 - A0
D10
D9
D8
D7
0C
<FINE GAIN>
FINE GAIN CONTROL (1 dB to 6 dB)
0
BITS
D6
D5
D4
D3
D2
D1
D0
0
0
<CUSTOM B>
CUSTOM PATTERN (UPPER 5 BITS)
D4 - D0
<CUSTOM B> Upper 5 bits of custom pattern <DATAOUT15>…<DATAOUT11>
D10-D8
000
001
010
011
100
101
110
<FINE GAIN> Fine gain control
0 dB gain (Full-scale range = 2.00 Vpp)
1 dB gain (Full-scale range = 1.78 Vpp)
2 dB gain (Full-scale range = 1.59 Vpp)
3 dB gain (Full-scale range = 1.42 Vpp)
4 dB gain (Full-scale range = 1.26 Vpp)
5 dB gain (Full-scale range = 1.12 Vpp)
6 dB gain (Full-scale range = 1.00 Vpp)
REGISTER
ADDRESS
A4 - A0
D10
D9
<OVRD>
0D
OVER-RIDE
0
BITE
Table 19. Serial Register F
BITS
D8
D7
D6
D5
D4
D3
<COARSE FALLING OR
0
BYTE-WISE
OR
BIT-WISE
MSB OR
LSB FIRST
GAIN>
COURSE
GAIN
RISING BIT
CLOCK
CAPTURE
0
ENABLE
EDGE
D2
D1
D0
14-BIT OR
16-BIT
SERIALIZE
DDR OR
SDR BIT
CLOCK
1-WIRE OR
2-WIRE
INTERFACE
D0
Interface selection
0
1 wire interface
1
2 wire interface
D1
Bit clock selection (only in 2-wire interface)
0
DDR bit clock
1
SDR bit clock
D2
Serialization factor selection
0
14X serialization
1
16X serialization
D4
Bit clock capture edge (only when SDR bit clock is selected, D1=1)
0
Capture data with falling edge of bit clock
1
Capture data with rising edge of bit clock
20
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS6245 ADS6244 ADS6243 ADS6242