ADS6245 Datasheet, PDF (15/76 Pages) Texas Instruments – DUAL CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS

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ADS6245, ADS6244
ADS6243, ADS6242
SLAS542A – MAY 2007 – REVISED JULY 2007
SERIAL INTERFACE
The ADC has a serial interface formed by pins SEN (serial interface enable), SCLK (serial interface clock),
SDATA (serial interface data) and RESET. Serial shift of bits into the device is enabled when SEN is low. Serial
data SDATA is latched at every falling edge of SCLK when SEN is active (low). The serial data is loaded into the
register at every 16th SCLK falling edge when SEN is low. In case the word length exceeds a multiple of 16 bits,
the excess bits are ignored. Data can be loaded in multiple of 16-bit words within a single active SEN pulse. The
interface can work with SCLK frequency from 20 MHz down to very low speeds (few hertz) and even with
non-50% duty cycle SCLK.
The first 5-bits of the 16-bit word are the address of the register while the next 11 bits are the register data.
Register Reset
After power-up, the internal registers must be reset to their default values. This can be done in one of two ways:
1. Either by applying a high-going pulse on RESET (of width greater than 10ns) OR
2. By applying software reset. Using the serial interface, set the <RST> bit in register 0x00 to high – this resets
the registers to their default values and then self-resets the <RST> bit to LOW.
When RESET pin is not used, it must be tied to LOW.
SDATA
SCLK
SEN
RESET
Register Address
Register Data
A4 A3 A2 A1 A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
t_(SCLK)
t_(DSU)
t_(DH)
t_(SLOADS)
t_(SLOADH)
Figure 4. Serial Interface Timing
T0109-03
Copyright © 2007, Texas Instruments Incorporated
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