TMS320DM641 Datasheet, PDF (46/171 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processors

Pin Assignments
Table 1−6. Terminal Functions (Continued)
SIGNAL
NAME
DM641
DM640
TYPE†
IPD/
IPU‡
DESCRIPTION
EMIFA (32-BIT) − BUS ARBITRATION
AHOLDA
N22
N22
O
IPU EMIFA hold-request-acknowledge to the host
AHOLD
W24 W24
I
IPU EMIFA hold request from the host
ABUSREQ
P22
P22
O
IPU EMIFA bus request output
EMIFA (32-BIT) − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL
AECLKIN
EMIFA external input clock. The EMIFA input clock (AECLKIN, CPU/4 clock,
H25
H25
I
IPD
or CPU/6 clock) is selected at reset via the pullup/pulldown resistors on the
AEA[20:19] pins.
AECLKIN is the default for the EMIFA input clock.
AECLKOUT2
J23
J23
O/Z
IPD
EMIFA output clock 2. Programmable to be EMIFA input clock (AECLKIN,
CPU/4 clock, or CPU/6 clock) frequency divided-by-1, -2, or -4.
AECLKOUT1
J26
J26
O/Z
IPD
EMIFA output clock 1 [at EMIFA input clock (AECLKIN, CPU/4 clock, or
CPU/6 clock) frequency].
AARE/
ASDCAS/
ASADS/ASRE
EMIFA asynchronous memory read-enable/SDRAM column-address
strobe/programmable synchronous interface-address strobe or read-enable
• For programmable synchronous interface, the RENEN field in the CE
Space Secondary Control Register (CExSEC) selects between ASADS
J25
J25
O/Z
IPU
and ASRE:
If RENEN = 0, then the ASADS/ASRE signal functions as the ASADS
signal.
If RENEN = 1, then the ASADS/ASRE signal functions as the ASRE
signal.
AAOE/
ASDRAS/
ASOE
J24
J24
O/Z
IPU
EMIFA asynchronous memory output-enable/SDRAM row-address
strobe/programmable synchronous interface output-enable
AAWE/
ASDWE/
ASWE
K26
K26
O/Z
IPU
EMIFA asynchronous memory write-enable/SDRAM
write-enable/programmable synchronous interface write-enable
ASDCKE
EMIFA SDRAM clock-enable (used for self-refresh mode).
L25
L25
O/Z
IPU • If SDRAM is not in system, ASDCKE can be used as a general-purpose
output.
ASOE3
R22
R22
O/Z
IPU
EMIFA synchronous memory output-enable for ACE3 (for glueless FIFO
interface)
AARDY
L22
L22
I
IPU Asynchronous memory ready input
† _{I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground}
‡ _{IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite}
supply rail, a 1-kΩ resistor should be used.)
§ _{These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.}
46 _SPRS222C
June 2003 − Revised August 2004