TMS320DM641 Datasheet, PDF (166/171 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processors

General-Purpose Input/Output (GPIO)
4.18.2 GPIO Peripheral Register Description(s)
HEX ADDRESS RANGE
01B0 0000
01B0 0004
01B0 0008
01B0 000C
01B0 0010
01B0 0014
01B0 0018
01B0 001C
01B0 0020
01B0 0024
01B0 0028 − 01B3 EFFF
Table 4−79. GP0 Registers
ACRONYM
GPEN
GPDIR
GPVAL
−
GPDH
GPHM
GPDL
GPLM
GPGC
GPPOL
−
REGISTER NAME
GP0 enable register
GP0 direction register
GP0 value register
Reserved
GP0 delta high register
GP0 high mask register
GP0 delta low register
GP0 low mask register
GP0 global control register
GP0 interrupt polarity register
Reserved
4.18.3 General-Purpose Input/Output (GPIO) Electrical Data/Timing
Table 4−80. Timing Requirements for GPIO Inputs^†‡ (see Figure 4−63)
−400
−500
NO.
−600
UNIT
MIN MAX
1 tw(GPIH)
2 tw(GPIL)
Pulse duration, GPIx high
Pulse duration, GPIx low
8P
ns
8P
ns
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.}
‡ _{The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DSP recognize the GPIx}
changes through software polling of the GPIO register, the GPIx duration must be extended to at least 12P to allow the DSP enough time to access
the GPIO register through the CFGBUS.
Table 4−81. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs^†
(see Figure 4−63)
NO.
PARAMETER
−400
−500
−600
UNIT
3 tw(GPOH) Pulse duration, GPOx high
4 tw(GPOL) Pulse duration, GPOx low
MIN MAX
24P − 8‡
ns
24P − 8‡
ns
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.}
‡ _{This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the GPIO}
is dependent upon internal bus activity.
GPIx
GPOx
2
1
4
3
Figure 4−63. GPIO Port Timing
166 _SPRS222C
June 2003 − Revised August 2004