TMS320DM641 Datasheet, PDF (143/171 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processors

Multichannel Buffered Serial Port (McBSP)
Table 4−50. Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 10b, CLKXP = 1^†‡ (see Figure 4−46)
−400
−500
NO.
−600
MASTER
SLAVE
MIN MAX
MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high
12
5 th(CKXH-DRV) Hold time, DR valid after CLKX high
4
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.}
‡ _{For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.}
2 − 12P
5 + 24P
UNIT
ns
ns
Table 4−51. Switching Characteristics Over Recommended Operating Conditions for McBSP as
SPI Master or Slave: CLKSTP = 10b, CLKXP = 1^†‡ (see Figure 4−46)
NO.
PARAMETER
1 th(CKXH-FXL)
2 td(FXL-CKXL)
Hold time, FSX low after CLKX high¶
Delay time, FSX low to CLKX low#
3 td(CKXL-DXV)
Delay time, CLKX low to DX valid
6
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX high
MASTER§
−400
−500
−600
SLAVE
MIN MAX
MIN
MAX
T−2 T+3
H − 2.5 H + 3
−2
4 12P + 3 20P + 17
UNIT
ns
ns
ns
H−2 H+3
ns
7 tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit
from FSX high
4P + 3 12P + 17 ns
8 td(FXL-DXV)
Delay time, FSX low to DX valid
8P + 2 16P + 17 ns
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.}
‡ _{For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.}
§ _{S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)}
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶ _{FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX}
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
# _{FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock}
(CLKX).
CLKX
1
FSX
7
6
DX
Bit 0
DR
Bit 0
2
8
4
Bit(n-1)
Bit(n-1)
3
(n-2)
5
(n-2)
(n-3)
(n-3)
(n-4)
(n-4)
Figure 4−46. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
June 2003 − Revised August 2004
SPRS222C ¹⁴³