TMS320C6748 Datasheet, PDF (46/242 Pages) Texas Instruments – Fixed/Floating-Point DSP

TMS320C6748 Fixed/Floating-Point DSP
SPRS590 – JUNE 2009
3.8.21 Universal Host-Port Interface (UHPI)
www.ti.com
Table 3-24. Universal Host-Port Interface (UHPI) Terminal Functions
SIGNAL
NAME
VP_DIN[7] / UHPI_HD[15] / UPP_CH1_D[15] / RMII_TXD[1]
VP_DIN[6] / UHPI_HD[14] / UPP_CH1_D[14] / RMII_TXD[0]
VP_DIN[5] / UHPI_HD[13] / UPP_CH1_D[13] / RMII_TXEN
VP_DIN[4] / UHPI_HD[12] / UPP_CH1_D[12] / RMII_RXD[1]
VP_DIN[3] / UHPI_HD[11] / UPP_CH1_D[11] / RMII_RXD[0]
VP_DIN[2] / UHPI_HD[10] / UPP_CH1_D[10] / RMII_RXER
VP_DIN[1] / UHPI_HD[9] / UPP_CH1_D[9] / RMII_MHZ_50_CLK
VP_DIN[0] / UHPI_HD[8] / UPP_CH1_D[8] / RMII_CRS_DV
VP_DIN[15]_VSYNC / UHPI_HD[7] / UPP_CH1_D[7]
VP_DIN[14]_HSYNC / UHPI_HD[6] / UPP_CH1_D[6]
VP_DIN[13]_FIELD / UHPI_HD[5] / UPP_CH1_D[5]
VP_DIN[12] / UHPI_HD[4] / UPP_CH1_D[4]
VP_DIN[11] / UHPI_HD[3] / UPP_CH1_D[3]
VP_DIN[10] / UHPI_HD[2] / UPP_CH1_D[2]
VP_DIN[9] / UHPI_HD[1] / UPP_CH1_D[1]
VP_DIN[8] / UHPI_HD[0] / UPP_CH1_D[0] / GP6[5]
UHPI_HCNTL0 / UPP_CH1_CLK / GP6[11]
UHPI_HCNTL1 / UPP_CH1_START / GP6[10]
UHPI_HHWIL / UPP_CH1_ENABLE / GP6[9]
UHPI_HRW / UPP_CH1_WAIT / GP6[8]
VP_CLKIN0 / UHPI_HCS / GP6[7] / UPP_2xTXCLK
VP_CLKIN1 / UHPI_HDS1 / GP6[6]
CLKOUT / UHPI_HDS2 / GP6[14]
UHPI_HINT / GP6[12]
UHPI_HRDY / GP6[13]
RESETOUT / UHPI_HAS / GP6[15]
NO.
U18
V16
R14
W16
V17
W17
W18
W19
V18
V19
U19
T16
R18
R19
R15
P17
U17
W15
TYPE ⁽¹⁾
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
U16
I
T15
I
W14
I
V15
I
T18
I
R16
I
R17
O
T17
I
PULL ⁽²⁾
CP[26]
CP[26]
CP[26]
CP[26]
CP[26]
CP[26]
CP[26]
CP[26]
CP[27]
CP[27]
CP[27]
CP[27]
CP[27]
CP[27]
CP[27]
CP[27]
CP[24]
CP[24]
CP[24]
CP[24]
CP[25]
CP[25]
CP[22]
CP[23]
CP[23]
CP[21]
POWER
GROUP ⁽³⁾
DESCRIPTION
C
C
C
C
C
C
C
C
UHPI data bus
C
C
C
C
C
C
C
C
C
UHPI access control
C
C
UHPI half-word
identification control
C
UHPI read/write
C
UHPI chip select
C
UHPI data strobe
C
C
UHPI host interrupt
C
UHPI ready
C
UHPI address strobe
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a
pull-up, an external pull-up can be used.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
46
Device Overview
Submit Documentation Feedback