TMS320C6748 Datasheet, PDF (152/242 Pages) Texas Instruments – Fixed/Floating-Point DSP

TMS320C6748 Fixed/Floating-Point DSP
SPRS590 – JUNE 2009
Table 6-73. Additional⁽¹⁾ SPI1 Slave Timings, 4-Pin Chip Select Option⁽²⁾⁽³⁾
NO.
25 t_{d(SCSL_SPC)S}
26 t_{d(SPC_SCSH)S}
27 t_{ena(SCSL_SOMI)S}
28 t_{dis(SCSH_SOMI)S}
PARAMETER
Required delay from SPI1_SCS asserted at slave to first SPI1_CLK edge at slave.
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Required delay from final SPI1_CLK edge before
SPI1_SCS is deasserted.
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid
Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI
1.2V
MIN
MAX
P+1.5
0.5M+P+4
P+4
0.5M+P+4
P+4
P+15
P+15
1.1V
MIN
MAX
P+1.5
0.5M+P+5
P+5
0.5M+P+5
P+5
P+17
P+17
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-68).
(2) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
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1.0V
MIN
MAX
P+1.5
0.5M+P+6
UNIT
ns
P+6
ns
0.5M+P+6
P+6
P+19
ns
P+19
ns
152 Peripheral Information and Electrical Specifications
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