TMS320C6748 Datasheet, PDF (141/242 Pages) Texas Instruments – Fixed/Floating-Point DSP

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NO.
23 t_{d(ENA_SPC)M}
TMS320C6748 Fixed/Floating-Point DSP
SPRS590 – JUNE 2009
Table 6-63. Additional SPI0 Master Timings, 5-Pin Option (continued)
PARAMETER
Delay from assertion of SPI0_ENA
low to first SPI0_CLK edge.⁽¹⁰⁾
Polarity = 0, Phase = 0,
to SPI0_CLK rising
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
1.2V
MIN
MAX
3P+5
0.5M+3P+5
3P+5
0.5M+3P+5
1.1V
MIN
MAX
3P+5
0.5M+3P+5
3P+5
0.5M+3P+5
1.0V
MIN
MAX
3P+6
UNIT
0.5M+3P+6
ns
3P+6
0.5M+3P+6
(10) If SPI0_ENA was initially deasserted high and SPI0_CLK is delayed.
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Peripheral Information and Electrical Specifications 141