DLPC350 Datasheet, PDF (46/50 Pages) Texas Instruments – DLP Digital Controller for the DLP4500 DMD

DLPC350
DLPS029A – APRIL 2013 – REVISED MAY 2013
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Figure 27. PLL Filter Layout
High frequency decoupling is required for both 1.2V and 1.8V PLL supplies and should be provided as close as
possible to each of the PLL supply package pins. It is recommended that decoupling capacitors be placed under
the package on the opposite side of the board. High quality, low-ESR, monolithic, surface mount capacitors
should be used. Typically 0.1 µF for each PLL supply should be sufficient. The length of a connecting trace
increases the parasitic inductance of the mounting and thus, where possible, there should be no trace, allowing
the via to butt up against the land itself. Additionally the connecting trance should be made as wide as possible.
Further improvement can be made by placing vias to the side of the capacitor lands or doubling the number of
vias.
The location of bulk decoupling depends on the system design. Typically a good ceramic capacitor in the 10 µF
range is adequate.
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