DLPC350 Datasheet, PDF (28/50 Pages) Texas Instruments – DLP Digital Controller for the DLP4500 DMD

DLPC350
DLPS029A – APRIL 2013 – REVISED MAY 2013
Port 2 Input Pixel Interface (FPD-Link Compatible LVDS Input)
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Table 9. Port 2 Input Pixel Interface (FPD-Link Compatible LVDS Input) Timing Requirements
f_clock
t_c
PARAMETER
Clock frequency, P2_CLK (LVDS input clock)
Cycle time, P2_CLK (LVDS input clock)
t_slew Clock or data slew rate
t_startup Link startup time (internal)
TEST CONDITIONS
f_pxck < 90 MHz
f_pxck > 90 MHz
MIN
MAX UNIT
20
90 MHz
11.1
50.0 ns
0.3
V/ns
0.5
1 ms
Extra Notes:
Minimize cross-talk and match traces on PCB as close as possible.
It is recommended to keep the Common Mode Voltage as close to 1.2V as possible.
It is recommended to keep the Absolute Input Differential Voltage as high as possible.
The LVDS open input detection is only related to a low common mode voltage; it is not related to a low
differential swing.
LVDS power 3.3V supply (VDD33_FPD) noise level should be below 100 mV_p-p.
LVDS power 1.2V supply (VDD12_FPD) noise level should be below 60 mV_p-p.
Figure 14. LVDS Timing Diagram
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