ADS61B29 Datasheet, PDF (46/61 Pages) Texas Instruments – 14-/12-Bit, 250-MSPS ADCs With Integrated Analog Buffer

ADS61B29
ADS61B49
SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com
FINE GAIN CONTROL
The ADS61B49/29 include gain settings that can be used to get improved SFDR performance (compared to no
gain) or to reduce the required full-scale input voltage. The gain is programmable from 0 dB to 6 dB (in 0.5-dB
steps). For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 9.
The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades about
0.5–1 dB. The SNR degradation is less at high input frequencies. As a result, the fine gain is useful at high input
frequencies as the SFDR improvement is significant with marginal degradation in SNR.
So, the fine gain can be used to trade-off between SFDR and SNR. Note that the default gain after reset is 0 dB.
Table 9. Full-Scale Range Across Gains
GAIN, dB
0
1
2
3
4
5
6
TYPE
Default after reset
Fine, programmable
FULL-SCALE, V_PP
2V
1.78
1.59
1.42
1.26
1.12
1.00
OFFSET CORRECTION
The ADS61B49/29 have an internal offset correction algorithm that estimates and corrects the dc offset up to ±10
mV. The correction can be enabled using the serial register bit <ENABLE OFFSET CORR>. Once enabled, the
algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the
correction loop is a function of the sampling clock frequency. The time constant can be controlled using register
bits <OFFSET CORR TIME CONSTANT> as described in Table 10.
After the offset is estimated, the correction can be locked in by setting <OFFSET CORR TIME CONSTANT> = 0.
Once locked, the last estimated value is used for offset correction every clock cycle. Note that offset correction is
disabled by default after a reset.
Figure 70 shows the time response of the offset correction algorithm, after it is enabled.
Table 10. Time Constant of Offset Correction Algorithm
<OFFSET CORR TIME CONSTANT> D3-D0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
TIME CONSTANT (T_CCLK), NUMBER OF
CLOCK CYCLES
256 k
512 k
1M
2M
4M
8M
16 M
32 M
64 M
128 M
256 M
512 M
Reserved
Reserved
Reserved
TIME CONSTANT, sec (T_CCLK x 1/F_s)⁽¹⁾
1 ms
2 ms
4 ms
8 ms
17 ms
33 ms
67 ms
134 ms
268 ms
536 ms
1.1 s
2.2 s
–
–
–
(1) Sampling frequency, F_s = 250 MSPS
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