ADS61B29 Datasheet, PDF (22/61 Pages) Texas Instruments – 14-/12-Bit, 250-MSPS ADCs With Integrated Analog Buffer

ADS61B29
ADS61B49
SLWS214A – OCTOBER 2008 – REVISED DECEMBER 2008 ......................................................................................................................................... www.ti.com
H)
A7–A0 IN HEX
D7
53
0
D6
<ENABLE OFFSET CORR>
Offset correction enable
D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
D6
<ENABLE OFFSET CORR>
0
Offset correction disabled
1
Offset correction enabled
I)
A7–A0 IN HEX
D7
55
D6
D5
<FINE GAIN>
D4
D3
D2
D1
D0
<OFFSET CORR TC> Offset correction time constant
D7–D4 <FINE GAIN> Gain programmability in 0.5-dB steps
0000
0-dB gain, default after reset
0001
0.5-dB gain
0010
1.0-dB gain
0011
1.5-dB gain
0100
2.0-dB gain
0101
2.5-dB gain
0110
3.0-dB gain
0111
3.5-dB gain
1000
4.0-dB gain
1001
4.5-dB gain
1010
5.0-dB gain
1011
5.5-dB gain
1100
6.0-dB gain
D3–D0
<OFFSET CORR TC> Time constant of correction loop in number of clock cycles. See Offset Correction in application
section.
0000
256 k
0001
512 k
0010
1M
0011
2M
0100
4M
0101
8M
0110
16 M
0111
32 M
1000
64 M
1001
128 M
1010
256 M
1011
512 M
1100 to 1111 Reserved
22
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