TMS320C6748_2 Datasheet, PDF (45/254 Pages) Texas Instruments – Fixed/Floating-Point DSP

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3.8.15 Multichannel Audio Serial Ports (McASP)
TMS320C6748 Fixed/Floating-Point DSP
SPRS590A – JUNE 2009 – REVISED AUGUST 2009
Table 3-18. Multichannel Audio Serial Ports Terminal Functions
SIGNAL
NAME
TYPE ⁽¹⁾
NO.
McASP0
AXR15 / EPWM0TZ[0] / ECAP2_APWM2 / GP0[7]
A4
I/O
AXR14 / CLKR1 / GP0[6]
B4
I/O
AXR13 / CLKX1 / GP0[5]
B3
I/O
AXR12 / FSR1 / GP0[4]
C4
I/O
AXR11 / FSX1 / GP0[3]
C5
I/O
AXR10 / DR1 / GP0[2]
D4
I/O
AXR9 / DX1 / GP0[1]
C3
I/O
AXR8 / CLKS1 / ECAP1_APWM1 / GP0[0] / PRU0_R31[8] E4
I/O
AXR7 / EPWM1TZ[0] / PRU0_R30[17] / GP1[15] /
PRU0_R31[7]
D2
I/O
AXR6 / CLKR0 / GP1[14] / MII_TXEN / PRU0_R31[6]
C1
I/O
AXR5 / CLKX0 / GP1[13] / MII_TXCLK
D3
I/O
AXR4 / FSR0 / GP1[12] / MII_COL
D1
I/O
AXR3 / FSX0 / GP1[11] / MII_TXD[3]
E3
I/O
AXR2 / DR0 / GP1[10] / MII_TXD[2]
E2
I/O
AXR1 / DX0 / GP1[9] / MII_TXD[1]
E1
I/O
AXR0 / ECAP0_APWM0 / GP8[7] / MII_TXD[0] / CLKS0 F3
I/O
AHCLKX / USB_REFCLKIN / UART1_CTS / GP0[10] /
PRU0_R31[17]
A3
I/O
ACLKX / PRU0_R30[19]/ GP0[14]/ PRU0_R31[21]
B1
I/O
AFSX / GP0[12] / PRU0_R31[19]
B2
I/O
AHCLKR / PRU0_R30[18] / UART1_RTS /GP0[11] /
PRU0_R31[18]
A2
I/O
ACLKR / PRU0_R30[20] / GP0[15]/ PRU0_R31[22]
A1
I/O
AFSR / GP0[13] / PRU0_R31[20]
C2
I/O
AMUTE / PRU0_R30[16] / UART2_RTS / GP0[9] /
PRU0_R31[16]
D5
I/O
PULL ⁽²⁾
CP[1]
CP[2]
CP[2]
CP[2]
CP[2]
CP[2]
CP[2]
CP[3]
CP[4]
CP[5]
CP[5]
CP[5]
CP[5]
CP[5]
CP[5]
CP[6]
CP[0]
CP[0]
CP[0]
CP[0]
CP[0]
CP[0]
CP[0]
POWER
GROUP ⁽³⁾
DESCRIPTION
A
A
A
A
A
A
A
A
McASP0 serial data
A
A
A
A
A
A
A
A
A
McASP0 transmit master clock
A
McASP0 transmit bit clock
A
McASP0 transmit frame sync
A
McASP0 receive master clock
A
McASP0 receive bit clock
A
McASP0 receive frame sync
A
McASP0 mute output
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a
pull-up, an external pull-up can be used.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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