TMS320C6748_2 Datasheet, PDF (133/254 Pages) Texas Instruments – Fixed/Floating-Point DSP

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TMS320C6748 Fixed/Floating-Point DSP
SPRS590A – JUNE 2009 – REVISED AUGUST 2009
Table 6-49. Timing Requirements for McBSP0 [1.0V]⁽¹⁾ (see Figure 6-33)
NO.
PARAMETER
1.0V
UNIT
MIN MAX
2 t_c(CKRX)
3 t_w(CKRX)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
5 t_su(FRH-CKRL) Setup time, external FSR high before CLKR low
CLKR/X ext
2P or
26.6 ^{(2) (3)}
ns
CLKR/X ext
P - 1⁽⁴⁾
ns
CLKR int
20
ns
CLKR ext
5
6 t_h(CKRL-FRH) Hold time, external FSR high after CLKR low
CLKR int
6
ns
CLKR ext
3
7 t_su(DRV-CKRL) Setup time, DR valid before CLKR low
CLKR int
20
ns
CLKR ext
5
8 t_h(CKRL-DRV) Hold time, DR valid after CLKR low
CLKR int
3
ns
CLKR ext
3
10 t_su(FXH-CKXL) Setup time, external FSX high before CLKX low
CLKX int
20
ns
CLKX ext
5
11 t_h(CKXL-FXH) Hold time, external FSX high after CLKX low
CLKX int
6
ns
CLKX ext
3
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) P = AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements.
(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
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Peripheral Information and Electrical Specifications 133