TMS320C6748_2 Datasheet, PDF (128/254 Pages) Texas Instruments – Fixed/Floating-Point DSP

TMS320C6748 Fixed/Floating-Point DSP
SPRS590A – JUNE 2009 – REVISED AUGUST 2009
www.ti.com
Table 6-45. Switching Characteristics for McASP0 (1.2V, 1.1V)⁽¹⁾
NO.
PARAMETER
1.2V
MIN
MAX
1.1V
UNIT
MIN
MAX
9 t_c(AHCLKRX)
Cycle time, AHCLKR/X
20
22
ns
10 t_w(AHCLKRX)
Pulse duration, AHCLKR/X high or low
AH – 2.5⁽²⁾
AH – 2.5⁽²⁾
ns
11 t_c(ACLKRX)
Cycle time, ACLKR/X
ACLKR/X int
20 ^{(3) (4)}
22^{(3) (4)}
ns
12 t_w(ACLKRX)
Pulse duration, ACLKR/X high or low ACLKR/X int
A – 2.5⁽⁵⁾
A – 2.5⁽⁵⁾
ns
13
t_{d(ACLKRX-AFSRX)}
Delay time, ACLKR/X transmit edge to
AFSX/R output valid⁽⁶⁾
ACLKR/X int
ACLKR/X ext input
ACLKR/X ext output
0
6
0
8
ns
2
13.5
2
14.5 ns
2
13.5
2
14.5 ns
14 t_{d(ACLKX-AXRV)}
Delay time, ACLKX transmit edge to
AXR output valid
ACLKR/X int
ACLKR/X ext input
ACLKR/X ext output
0
6
0
8
ns
2
13.5
2
14.5 ns
2
13.5
2
14.5 ns
Disable time, ACLKR/X transmit edge to ACLKR/X int
15
t_{dis(ACLKX-AXRHZ)}
AXR high impedance following last data
bit
ACLKR/X ext
0
6
0
8
ns
2
13.5
2
14.5 ns
(1) McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AH = (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(3) P = SYSCLK2 period
(4) This timing is limited by the timing shown or 2P, whichever is greater.
(5) A = (ACLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(6) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
Table 6-46. Switching Characteristics for McASP0 (1.0V)⁽¹⁾
NO.
PARAMETER
9 t_c(AHCLKRX)
Cycle time, AHCLKR/X
10 t_w(AHCLKRX)
Pulse duration, AHCLKR/X high or low
11 t_c(ACLKRX)
Cycle time, ACLKR/X
ACLKR/X int
12 t_w(ACLKRX)
Pulse duration, ACLKR/X high or low
ACLKR/X int
ACLKR/X int
13 t_{d(ACLKRX-AFSRX)} Delay time, ACLKR/X transmit edge to AFSX/R output valid⁽⁶⁾ ACLKR/X ext input
ACLKR/X ext output
ACLKR/X int
14 t_{d(ACLKX-AXRV)} Delay time, ACLKX transmit edge to AXR output valid
ACLKR/X ext input
ACLKR/X ext output
15
t_{dis(ACLKX-AXRHZ)}
Disable time, ACLKR/X transmit edge to AXR high
impedance following last data bit
ACLKR/X int
ACLKR/X ext
(1) McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AH = (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(3) P = SYSCLK2 period
(4) This timing is limited by the timing shown or 2P, whichever is greater.
(5) A = (ACLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(6) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
1.0V
MIN
MAX
26.6
AH – 2.5⁽²⁾
26.6 ^{(3) (4)}
A – 2.5⁽⁵⁾
0
10
2
19
2
19
0
10
2
19
2
19
0
10
2
19
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
128 Peripheral Information and Electrical Specifications
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