TMS320VC5501 Datasheet, PDF (44/193 Pages) Texas Instruments – TMS320VC5501 Fixed-Point Digital Signal Processor

Functional Overview
Table 3−4 lists the individual routing of the EMIF and PGPIO signals to the external parallel address, data, and
control buses.
Table 3−4. TMS320VC5501 Routing of Parallel Port Mux Signals
PIN
A[17:2]
A[21:18]
D[31:16]
D[15:0]
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
PARALLEL/HOST PORT MUX MODE = 0
(PGPIO)
Address Bus
Reserved
PGPIO[3:0]
Data Bus
PGPIO[19:4]
Reserved
Control Bus
PGPIO20
PGPIO21
PGPIO22
PGPIO23
PGPIO24
PGPIO25
PGPIO26
PGPIO27
PGPIO28
PGPIO29
PGPIO30
PGPIO31
PGPIO32
PGPIO33
PGPIO34
PGPIO35
PARALLEL/HOST PORT MUX MODE = 1
(FULL EMIF)
EMIF.A[17:2]
EMIF.A[21:18]
EMIF.D[31:16]
EMIF.D[15:0]
EMIF.ARE/SADS/SDCAS/SRE
EMIF.AOE/SOE/SDRAS
EMIF.AWE/SWE/SDWE
EMIF.ARDY
EMIF.CE0
EMIF.CE1
EMIF.CE2
EMIF.CE3
EMIF.BE0
EMIF.BE1
EMIF.BE2
EMIF.BE3
EMIF.SDCKE
EMIF.SOE3
EMIF.HOLD
EMIF.HOLDA
44 SPRS206H
December 2002 − Revised November 2004