TMS320VC5501 Datasheet, PDF (151/193 Pages) Texas Instruments – TMS320VC5501 Fixed-Point Digital Signal Processor

Electrical Specifications
5.7.3 Synchronous DRAM Timings
Table 5−13 and Table 5−14 assume testing over recommended operating conditions (see Figure 5−13
through Figure 5−20).
Table 5−13. Synchronous DRAM Cycle Timing Requirements
NO.
SD6 tsu(EDV-EKO1H)
SD7 th(EKO1H-EDV)
Setup time, read EMIF.Dx valid before ECLKOUT1 high
Hold time, read EMIF.Dx valid after ECLKOUT1 high
MIN MAX
2
2
UNIT
ns
ns
Table 5−14. Synchronous DRAM Cycle Switching Characteristics
NO.
PARAMETER
SD1
SD2
SD3
SD4
SD5
SD8
SD9
SD10
SD11
SD12
SD13
td(EKO1H-CEV)
td(EKO1H-BEV)
td(EKO1H-BEIV)
td(EKO1H-EAV)
td(EKO1H-EAIV)
td(EKO1H-CASV)
td(EKO1H-EDV)
td(EKO1H-EDIV)
td(EKO1H-WEV)
td(EKO1H-RASV)
td(EKO1H-CKEV)
Delay time, ECLKOUT1 high to EMIF.CEx valid/invalid
Delay time, ECLKOUT1 high to EMIF.BEx valid
Delay time, ECLKOUT1 high to EMIF.BEx invalid
Delay time, ECLKOUT1 high to EMIF.Ax valid
Delay time, ECLKOUT1 high to EMIF.Ax invalid
Delay time, ECLKOUT1 high to EMIF.SDCAS valid
Delay time, ECLKOUT1 high to EMIF.Dx valid
Delay time, ECLKOUT1 high to EMIF.Dx invalid
Delay time, ECLKOUT1 high to EMIF.SDWE valid
Delay time, ECLKOUT1 high to EMIF.SDRAS valid
Delay time, ECLKOUT1 high to EMIF.SDCKE valid
MIN MAX UNIT
0.8
7 ns
7 ns
0.8
ns
7 ns
0.8
ns
0.8
7 ns
7 ns
0.8
ns
0.8
7 ns
0.8
7 ns
0.8
7 ns
READ
ECLKOUT1
EMIF.CEx
EMIF.BE[3:0]
EMIF.A[21:13]
EMIF.A[11:2]
EMIF.A12
EMIF.D[31:0]
SD1
SD1
SD2
SD3
BE1
BE2
BE3
BE4
SD4
SD5
Bank
SD4
SD5
Column
SD4
SD5
SD6
SD7
D1
D2
D3
D4
EMIF.AOE/SOE/SDRAS†
EMIF.ARE/SADS/
SDCAS/SRE†
SD8
SD8
EMIF.AWE/SWE/SDWE†
† _{EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and}
EMIF.SDRAS, respectively, during SDRAM accesses.
Figure 5−13. SDRAM Read Command (CAS Latency 3)
December 2002 − Revised November 2004
SPRS206H 151