TMS320VC5501 Datasheet, PDF (20/193 Pages) Texas Instruments – TMS320VC5501 Fixed-Point Digital Signal Processor

Introduction
Table 2−3. 176-Pin PGF Low-Profile Quad Flatpack Pin Assignments^†‡
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
SIGNAL NAME
GPIO6
GPIO4
GPIO2
GPIO1
GPIO0
TIM1
TIM0
INT0
CVDD
INT1
INT2
DVDD
INT3
NMI/WDTOUT
IACK
VSS
CLKR0
DR0
FSR0
CLKX0
CVDD
DX0
FSX0
CLKR1
DR1
FSR1
DX1
CLKX1
VSS
FSX1
TEST§
NC
CVDD
RX
GPIO5
DVDD
TX
GPIO3
VSS
SCL
SDA
HC1
HC0
HCS
PIN NO.
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
SIGNAL NAME
HCNTL1
HCNTL0
VSS
HR/W
HDS2
CVDD
HDS1
HRDY
DVDD
CLKOUT
XF
VSS
C15
C14
HINT
PVDD
NC
X1
X2/CLKIN
EMIFCLKS
VSS
C13
C12
C11
C10
C9
C8
C7
VSS
ECLKIN
ECLKOUT2
ECLKOUT1
CVDD
C6
C5
DVDD
C4
C3
VSS
C2
C1
C0
A21
A20
PIN NO.
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
SIGNAL NAME
A19
A18
VSS
A17
A16
DVDD
A15
A14
VSS
A13
A12
CVDD
A11
A10
A9
A8
DVDD
A7
A6
A5
VSS
A4
A3
A2
CVDD
D31
D30
D29
VSS
D28
D27
D26
CVDD
D25
D24
DVDD
D23
D22
D21
D20
D19
VSS
D18
D17
PIN NO.
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
† _{CVDD is core VDD , DVDD is I/O VDD , and PVDD is PLL VDD .}
‡ _{NC indicates “no connect”.}
§ _{The TEST pin is reserved for internal testing. It should be left unconnected.}
¶ _{The GPIO7 pin must be low at the rising edge of the reset signal for the device to operate properly.}
SIGNAL NAME
D16
D15
D14
D13
D12
D11
D10
D9
DVDD
D8
D7
VSS
D6
D5
D4
CVDD
D3
D2
D1
D0
VSS
EMU1/OFF
EMU0
TDO
VSS
TDI
TRST
TCK
TMS
RESET
HPIENA
HD7
CVDD
HD6
HD5
DVDD
HD4
HD3
CVDD
HD2
HD1
VSS
HD0
GPIO7¶
20 SPRS206H
December 2002 − Revised November 2004