THS7376 Datasheet, PDF (44/61 Pages) Texas Instruments – 4-Channel Video Amplifier with One SD and Three HD 8th-Order Filters with 6-dB Gain

THS7376
SBOS692 – JUNE 2013
www.ti.com
INPUT MODE OF OPERATION: AC BIAS
Sync-tip clamps work very well for signals that have horizontal or vertical syncs associated with them; however,
some video signals do not have a sync embedded within the signal. If ac-coupling of these signals is desired,
then using a dc bias is desired to properly set the dc operating point within the device. This function is easily
accomplished with the THS7376 by simply adding an external pull-up resistor to the positive power supply, as
shown in Figure 133.
V_S+
V_S+
Input
C_IN
0.1 mF
R_PU
Input
Pin
800 kW
Internal
Circuitry
Level
Shift
Figure 133. AC-Bias Input Mode Circuit Configuration
The dc voltage appearing at the input pin is equal to Equation 1:
V =V
800 kW
DC
S
800
kW
+
R
PU
(1)
The device allowable input range is approximately 0 V to (V_S+ – 1.5 V), allowing for a very wide input voltage
range. As such, the input dc bias point is very flexible, with the output dc bias point being the primary factor. For
example, if the output dc bias point is desired to be 1.6 V on a 3.3-V supply, then the input dc bias point should
be (1.6 V – 210 mV) / 2 = 0.695 V. Thus, the pull-up resistor calculates to approximately 3 MΩ, resulting in
0.694 V. If the output dc-bias point is desired to be 1.6 V with a 5-V power supply, then the pull-up resistor
calculates to approximately 4.99 MΩ.
Keep in mind that the internal 800-kΩ resistor has approximately a ±20% variance. As such, the calculations
should take this variance into account. For the 0.644-V example above, using an ideal 3.3-MΩ resistor, the input
dc bias voltage is approximately 0.694 V ±0.1 V.
The value of the output bias voltage is very flexible and is left to each individual design. The signal must not clip
or saturate the video signal. Thus, TI recommends ensuring the output bias voltage is between 0.9 V and (V_S+ –
1 V). For 100% color-saturated CVBS or signals with Macrovision^®, the CVBS signal can reach up to 1.23 V_PP at
the input, or 2.46 V_PP at the device output. In contrast, other signals are typically 1 V_PP or 0.7 V_PP at the input
(which translates to an output voltage of 2 V_PP or 1.4 V_PP). The output bias voltage must account for a worst-
case situation, depending on the signals involved.
One other issue that must be taken into account is that the dc-bias point is a function of the power supply. As
such, there is an impact on system PSRR. To help reduce this impact, the input capacitor combines with the pull-
up resistance to function as a low-pass filter. Additionally, the time to charge the capacitor to the final dc bias
point is a function of the pull-up resistor and the input capacitor size. Lastly, the input capacitor forms a high-pass
filter with the parallel impedance of the pull-up resistor and the 800-kΩ resistor. In general, keep this high-pass
filter at approximately 3 Hz to minimize any potential droop on a P’_B or P’_R signal. A 0.1-μF input capacitor with a
3-MΩ pull-up resistor equates to approximately a 2.5-Hz high-pass corner frequency.
This mode of operation is recommended for use with chroma (C’), P’_B, P’_R, U’, and V’ signals. This method can
also be used with sync signals if desired. The benefit of using the STC function over the ac-bias configuration on
embedded sync signals is that the STC maintains a constant back-porch voltage as opposed to a back-porch
voltage that fluctuates depending on the video content. Because the high-pass corner frequency is a very low
2.5 Hz, the impact on the video signal is negligible relative to the STC configuration.
One question may arise over the P’_B and P’_R channels. For 480i, 576i, 480p, and 576p signals, a sync may or
may not be present. If no sync exists within the signal, then ac-bias is the preferred method to ac-couple the
signal.
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