THS7376 Datasheet, PDF (42/61 Pages) Texas Instruments – 4-Channel Video Amplifier with One SD and Three HD 8th-Order Filters with 6-dB Gain

THS7376
SBOS692 – JUNE 2013
www.ti.com
INPUT MODE OF OPERATION: AC SYNC TIP CLAMP
Some video DACs or encoders are not referenced to ground but rather to the positive power supply. The
resulting video signals are generally at too great a voltage for a dc-coupled video buffer to function properly. To
account for this scenario, the device incorporates a sync-tip clamp (STC) circuit. This function requires a
capacitor (nominally 0.1 μF) to be in series with the input. Although the term sync-tip-clamp is used throughout
this document, note that the device is probably better termed as a dc restoration circuit based on how this
function is performed. This circuit is an active clamp circuit and not a passive diode clamp function.
The input to the THS7376 has an internal control loop that sets the lowest input applied voltage to clamp at
ground (0 V). By setting the reference at 0 V, the device allows a dc-coupled input to also function. Therefore,
the STC is considered transparent because it does not operate unless the input signal goes below ground. The
signal then goes through the same 105-mV level shifter, resulting in an output voltage low level of 210 mV. If the
input signal tries to go below 0 V, the THS7376 internal control loop sources up to 6 mA of current to increase
the input voltage level on the device input side of the coupling capacitor. As soon as the voltage goes above the
0-V level, the loop stops sourcing current and becomes very high impedance.
One of the concerns about the sync-tip-clamp level is how the clamp reacts to a sync edge that has
overshoot—common in VCR signals, noise, DAC overshoot, or reflections found in poor printed circuit board
(PCB) layouts. Ideally, the STC should not react to the overshoot voltage of the input signal. Otherwise, this
response could result in clipping on the rest of the video signal because the response may raise the bias voltage
too much.
To help minimize this input signal overshoot problem, the control loop in the THS7376 has an internal low-pass
filter (LPF), as shown in Figure 132. This filter reduces the response time of the STC circuit. This delay is a
function of how far the voltage is below ground, but in general there is approximately a 400-ns delay for the SD
channel filters and approximately a 150-ns delay for the HD filters. The effect of this filter is to slow down the
response of the control loop so as not to clamp on the input overshoot voltage but rather on the flat portion of the
sync signal.
Input
0.1 mF ^Input
Pin
V_S+
V_S+
STC LPF
g_m
800 kW
Internal
Circuitry
Level
Shift
Figure 132. Equivalent AC Sync-Tip-Clamp Input Circuit
As a result of this delay, the sync signal may have an apparent voltage shift. The amount of shift depends on the
amount of droop in the signal as dictated by the input capacitor and the STC current flow. Because sync is used
primarily for timing purposes with syncing occurring on the edge of the sync signal, this shift is transparent in
most systems.
While this feature may not fully eliminate overshoot issues on the input signal, in cases of extreme overshoot or
ringing, the STC system should help minimize improper clamping levels. As an additional method to help
minimize this issue, an external capacitor (for example, 10 pF to 47 pF) to ground in parallel with the external
termination resistors can help filter overshoot problems.
Note that this STC system is dynamic and does not rely upon timing in any way. The system only depends on
the voltage that appears at the input pin at any given point in time. STC filtering helps minimize level shift
problems associated with switching noises or very short spikes on the signal line. This architecture helps ensure
a very robust STC system.
42
Submit Documentation Feedback
Product Folder Links: THS7376
Copyright © 2013, Texas Instruments Incorporated