PCI1410A Datasheet, PDF (44/140 Pages) Texas Instruments – PC Card Controllers

All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a start
condition, which is signaled when the SDA line transitions to a low state while SCL is in the high state, as illustrated
in Figure 3–10. The end of a requested data transfer is indicated by a stop condition, which is signaled by a low-to-high
transition of SDA while SCL is in the high state, as shown in Figure 3–10. Data on SDA must remain stable during
the high state of the SCL signal, as changes on the SDA signal during the high state of SCL are interpreted as control
signals, that is, a start or a stop condition.
SDA
SCL
Start
Condition
Stop
Condition
Data Line Stable, Change of
Data Valid
Data Allowed
Figure 3–10. Serial Bus Start/Stop Conditions and Bit Transfers
Data is transferred serially in 8-bit bytes. The number of bytes that can be transmitted during a data transfer is
unlimited; however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by
the receiver pulling the SDA signal low so that it remains low during the high state of the SCL signal. Figure 3–11
illustrates the acknowledge protocol.
SCL From
Master
1
2
3
7
8
9
SDA Output
By Transmitter
SDA Output
By Receiver
Figure 3–11. Serial Bus-Protocol Acknowledge
The PCI1410A device is a serial bus master; all other devices connected to the serial bus external to the PCI1410A
device are slave devices. As the bus master, the PCI1410A device drives the SCL clock at nearly 100 kHz during
bus cycles and places SCL in a high-impedance state (zero frequency) during idle states.
Typically, the PCI1410A device masters byte reads and byte writes under software control. Doubleword reads are
performed by the serial EEPROM initialization circuitry upon a PCI reset, and may not be generated under software
control. See Section 3.6.3, Serial Bus EEPROM Application, for details on how the PCI1410A device automatically
loads the subsystem identification and other register defaults through a serial bus EEPROM.
Figure 3–12 illustrates a byte write. The PCI1410A device issues a start condition and sends the 7-bit slave device
address and the command bit 0. A 0 in the R/W command bit indicates that the data transfer is a write. The slave
device acknowledges if it recognizes the address. If there is no acknowledgment received by the PCI1410A device,
an appropriate status bit is set in the serial bus control and status register (PCI offset B3h, see Section 4.50). The
word address byte is then sent by the PCI1410A device and another slave acknowledgment is expected. The
PCI1410A device then delivers the data byte, MSB first, and expects a final acknowledgment before issuing the stop
condition.
3–12