PCI1410A Datasheet, PDF (42/140 Pages) Texas Instruments – PC Card Controllers

3.5.10 PC Card-16 PC/PCI DMA
Some chip sets provide a way for legacy I/O devices to do DMA transfers on the PCI bus. In the PC/PCI DMA protocol,
the PCI1410A device acts as a PCI target device to certain DMA-related I/O addresses. The PCI1410A PCREQ and
PCGNT signals are provided as a point-to-point connection to a chipset supporting PC/PCI DMA. The PCREQ and
PCGNT signals may be routed to the MFUNC2 and MFUNC5 terminals, respectively. See Section 4.30, Multifunction
Routing Register, for details on configuring the multifunction terminals.
Under the PC/PCI protocol, a PCI DMA slave device (such as the PCI1410A device) requests a DMA transfer on a
particular channel using a serialized protocol on PCREQ. The I/O DMA bus master arbitrates for the PCI bus and
grants the channel through a serialized protocol on PCGNT when it is ready for the transfer. The I/O cycle and memory
cycles are then presented on the PCI bus, which performs the DMA transfers similarly to legacy DMA master devices.
PC/PCI DMA is enabled for each PC Card-16 slot by setting bit 19 (CDREQEN) in the respective system control
register (PCI offset 80h, see Section 4.29). On power up, this bit is reset and the card PC/PCI DMA is disabled. Bit 3
(CDMA_EN) of the system control register is a global enable for PC/PCI DMA, and is set at power up and never
cleared if the PC/PCI DMA mechanism is implemented. The desired DMA channel for each PC Card-16 slot must
be configured through bits 18–16 (CDMACHAN field) in the system control register. The channels are configured as
indicated in Table 3–3.
Table 3–3. PC/PCI Channel Assignments
SYSTEM CONTROL
REGISTER
BIT 18
0
0
0
0
1
1
1
1
BIT 17
0
0
1
1
0
0
1
1
BIT16
0
1
0
1
0
1
0
1
DMA CHANNEL
CHANNEL TRANSFER
DATA WIDTH
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
8-bit DMA transfers
8-bit DMA transfers
8-bit DMA transfers
8-bit DMA transfers
Not used
16-bit DMA transfers
16-bit DMA transfers
16-bit DMA transfers
As in distributed DMA, the PC Card terminal mapped to DREQ must be configured through socket DMA register 0
(PCI offset 94h, see Section 4.35). The data transfer width is a function of channel number, and the DMA slave
registers are not used. When a DREQ is received from a PC Card and the channel has been granted, the PCI1410A
device decodes the I/O addresses listed in Table 3–4 and performs actions dependent upon the address.
Table 3–4. I/O Addresses Used for PC/PCI DMA
DMA I/O ADDRESS
00h
04h
C0h
C4h
DMA CYCLE TYPE
Normal
Normal TC
Verify
Verify TC
TERMINAL COUNT
0
1
0
1
PCI CYCLE TYPE
I/O read/write
I/O read/write
I/O read
I/O read
When the PC/PCI DMA is used as a PC Card-16 DMA mechanism, it may not provide the performance levels of DMA;
however, the design of a PCI target implementing PC/PCI DMA is considerably less complex. No bus master state
machine is required to support PC/PCI DMA, since the DMA control is centralized in the chipset. This DMA scheme
often is referred to as centralized DMA for this reason.
3.5.11 CardBus Socket Registers
The PCI1410A device contains all registers for compatibility with the PC Card Standard. These registers exist as the
CardBus socket registers and are listed in Table 3–5.
3–10