PCI1410A Datasheet, PDF (34/140 Pages) Texas Instruments – PC Card Controllers

3.2 I/O Characteristics
Figure 3–2 shows a 3-state bidirectional buffer. Section 8.2, Recommended Operating Conditions, provides the
electrical characteristics of the inputs and outputs.
NOTE: The PCI1410A device meets the ac specifications of the PC Card Standard and PCI
Local Bus Specification.
Tied for Open Drain
OE
VCCP
Pad
Figure 3–2. 3-State Bidirectional Buffer
NOTE: Unused pins (input or I/O) must be held high or low to prevent them from floating.
3.3 Clamping Voltages
The clamping voltages are set to match whatever external environment the PCI1410A device is interfaced with: 3.3 V
or 5 V. The I/O sites can be pulled through a clamping diode to a voltage rail that protects the core from external
signals. The core power supply always is 3.3 V and is independent of the clamping voltages. For example, PCI
signaling can be either 3.3 V or 5 V, and the PCI1410A device must reliably accommodate both voltage levels. This
is accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage applied. If a
system designer desires a 5-V PCI bus, V_CCP can be connected to a 5-V power supply.
The PCI1410A device requires three separate clamping voltages because it supports a wide range of features. The
three voltages are listed and defined in Section 8.2, Recommended Operating Conditions.
3.4 Peripheral Component Interconnect (PCI) Interface
The PCI1410A device is fully compliant with the PCI Local Bus Specification. The PCI1410A device provides all
required signals for PCI master or slave operation, and can operate in either a 5-V or 3.3-V signaling environment
by connecting the V_CCP terminals to the desired voltage level. In addition to the mandatory PCI signals, the PCI1410A
device provides the optional interrupt signal INTA.
3.4.1 PCI Bus Lock (LOCK)
The bus-locking protocol defined in the PCI Local Bus Specification is not highly recommended, but is provided on
the PCI1410A device as an additional compatibility feature. The PCI LOCK signal can be routed to the MFUNC4
terminal via the multifunction routing register. See Section 4.30, Multifunction Routing Register, for details. Note that
the use of LOCK is supported only by PCI-to-CardBus bridges in the downstream direction (away from the processor).
PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted,
nonexclusive transactions can proceed to an address that currently is not locked. A grant to start a transaction on
the PCI bus does not guarantee control of LOCK; control of LOCK is obtained under its own protocol. It is possible
for different initiators to use the PCI bus while a single master retains ownership of LOCK. Note that the CardBus
signal for this protocol is CBLOCK to avoid confusion with the bus clock.
An agent may need to do an exclusive operation because a critical access to memory might be broken into several
transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by
PCI to be 16 bytes, aligned. The LOCK protocol defined by the PCI Local Bus Specification allows a resource lock
without interfering with nonexclusive real-time data transfer, such as video.
The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario,
the arbiter will not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A complete
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