DAC5682Z_09 Datasheet, PDF (41/59 Pages) Texas Instruments – 16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC)

DAC5682Z
www.ti.com ........................................................................................................................................................ SLLS853C – AUGUST 2007 – REVISED JUNE 2009
DLL OPERATION
The DAC5682Z provides a digital Delay Lock Loop (DLL) to skew the LVDS data clock (DCLK) relative to the
data bits, D[15:0] and SYNC, in order to maintain proper setup and hold timing. Since the DLL operates
closed-loop, it requires a stable DCLK to maintain delay lock. Refer to the description of DLL_ifixed(2:0) and
DLL_delay(3:0) control bits in the CONFIG10 register. Prior to initializing the DLL, the DLL_ifixed value should
be programmed to match the expected DCLK frequency range. To initialize the DLL, refer to the DLL_Restart
programming bit in the CONFIG8 register. After initialization, the status of the DLL can be verified by reading the
DLL_Lock bit from STATUS0. See Startup Sequence below.
RECOMMENDED STARTUP SEQUENCE
The following startup sequence is recommended to initialize the DAC5682Z:
1. Supply all 1.8V (CLKVDD, DVDD, VFUSE) voltages simultaneously followed by all 3.3V (AVDD and IOVDD)
voltages.
2. Provide stable CLKIN/C clock.
3. Toggle RESETB pin for a minimum 25 nSec active low pulse width.
4. Program all desired SIF registers. Set DLL_Restart bit during this write cycle. The CONFIG10 register value
should match the corresponding DCLKP/N frequency range in the Electrical Characteristics table.
5. Provide stable DCLKP/N clock. (This can also be provided earlier in the sequence)
6. Clear the DLL_Restart bit when the DCLKP/N clock is expected to be stable.
7. Verify the status of DLL_Lock and repeat until set to ‘1’. DLL_Lock can be monitored by reading the
STATUS0 register or by monitoring the SDO pin in 3-wire SIF mode. (See description for CONFIG14
SDO_func_sel.)
8. Enable transmit of data by asserting the LVDS SYNCP/N input or setting CONFIG3 SW_sync bit. (See
description for CONFIG3 SW_sync and SW_sync_sel) The SYNC source must be held at a logic ‘1’ to
enable data flow through the DAC. If multiple DAC devices require synchronization, refer to the
"Recommended Multi-DAC Synchronization Procedure" below.
9. Provide data flow to LVDS D[15:0]P/N pins. If using the LVDS SYNCP/N input, data can be input
simultaneous with the logic ‘1’ transition of SYNCP/N.
RECOMMENDED MULTI-DAC SYNCHRONIZATION PROCEDURE
The DAC5682Z provides a mechanism to synchronize multiple DAC devices in a system. The procedure has two
steps involving control of the CONFIG5 clkdiv_sync_dis and FIFO_sync_dis bits as well as external control of
the LVDS SYNCP/N input. (All DACs involved need to be configured to accept the external SYNCP/N input and
not "software" sync mode).
1. Synchronize Clock Dividers (for each DAC):
a. Set CONFIG5 clkdiv_sync_dis = 0.
b. Set CONFIG5 FIFO_sync_dis = 0.
c. Toggle SYNCP/N input to all DACs simultaneously (same input to all DACs).
2. Synchronize FIFO pointers (for each DAC):
a. Set CONFIG5 clkdiv_sync_dis = 1 (Disable clock divider re-sync).
b. Set CONFIG5 FIFO_sync_dis = 0 (Keep same as step 1).
c. Wait a minimum of 50 CLKIN cycles from previous SYNCP/N toggle. In practice, the time required to
write the above register value will typically occupy more than 50 cycles.
d. Assert SYNCP/N input and hold at '1' to all DACs simultaneously. Holding this at '1' is effectively the
TXENABLE for the chip so data will be output on the analog pins.
3. After the normal pipeline delay of the device, the outputs of all DACs will be synchronized to within ±1 DAC
clock cycle.
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): DAC5682Z
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