DAC5682Z_09 Datasheet, PDF (1/59 Pages) Texas Instruments – 16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC)

DAC5682Z
www.ti.com ........................................................................................................................................................ SLLS853C – AUGUST 2007 – REVISED JUNE 2009
16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DUAL-CHANNEL
DIGITAL-TO-ANALOG CONVERTER (DAC)
FEATURES
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• 16-Bit Digital-to-Analog Converter (DAC)
• 1.0 GSPS Update Rate
• 16-Bit Wideband Input LVDS Data Bus
– 8 Sample Input FIFO
– Interleaved I/Q data for Dual-DAC Mode
• High Performance
– 73 dBc ACLR WCDMA TM1 at 180 MHz
• 2x-32x Clock Multiplying PLL/VCO
• 2x or 4x Interpolation Filters
– Stopband Transition 0.4–0.6 Fdata
– Filters Configurable in Either Low-Pass or
High-Pass Mode
– Allows Selection of Higher Order Image
• Fs/4 Coarse Mixer
• On Chip 1.2 V Reference
• Differential Scalable Output: 2 to 20 mA
• Package: 64-Pin 9 × 9 mm QFN
APPLICATIONS
• Cellular Base Stations
• Broadband Wireless Access (BWA)
• WiMAX 802.16
• Fixed Wireless Backhaul
• Cable Modem Termination System (CMTS)
DESCRIPTION
The DAC5682Z is a dual-channel 16-bit 1.0 GSPS
digital-to-analog converter (DAC) with wideband
LVDS data input, integrated 2x/4x interpolation filters,
on-board clock multiplier and internal voltage
reference. The DAC5682Z offers superior linearity,
noise, crosstalk and PLL phase noise performance.
The DAC5682Z integrates a wideband LVDS port
with on-chip termination. Full-rate input data can be
transferred to a single DAC channel, or half-rate and
1/4-rate input data can be interpolated by on-board
2x or 4x FIR filters. Each interpolation FIR is
configurable in either Low-Pass or High-Pass mode,
allowing selection of a higher order output spectral
image. An on-chip delay lock loop (DLL) simplifies
LVDS interfacing by providing skew control for the
LVDS input data clock.
The DAC5682Z allows both complex or real output.
An optional Fs/4 coarse mixer in complex mode
provides coarse frequency upconversion and the dual
DAC output produces a complex Hilbert Transform
pair. An external RF quadrature modulator then
performs the final single sideband up-conversion.
The DAC5682Z is characterized for operation over
the industrial temperature range of –40°C to 85°C
and is available in a 64-pin QFN package. Other
single-channel members of the family include the
interpolating DAC5681Z and non-interpolating
DAC5681.
T_A
–40°C to 85°C
ORDER CODE
DAC5682ZIRGCT
DAC5682ZIRGCR
ORDERING INFORMATION
PACKAGE DRAWING/TYPE^(1)(2)(3)
TRANSPORT MEDIA
RGC / 64QFN Quad Flatpack
No-Lead
Tape and Reel
Tape and Reel
QUANTITY
250
2000
(1) Thermal Pad Size: 7,4 mm × 7,4 mm
(2) MSL Peak Temperature: Level-3-260C-168 HR
(3) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2009, Texas Instruments Incorporated