DAC5682Z_09 Datasheet, PDF (3/59 Pages) Texas Instruments – 16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC)

DAC5682Z
www.ti.com ........................................................................................................................................................ SLLS853C – AUGUST 2007 – REVISED JUNE 2009
DAC5682Z
RGC PACKAGE
(TOP VIEW)
CLKVDD 1
CLKIN 2
CLKINC 3
GND 4
SYNCP 5
SYNCN ⁶
D15P 7
D15N 8
IOVDD 9
DVDD 10
D14P 11
D14N 12
D13P 13
D13N 14
D12P 15
D12N 16
DAC5682Z
48 SDENB
47 SCLK
46 SDIO
45 SDO
44 VFUSE
43 D0N
42 D0P
41 D1N
40 D1P
39 DVDD
38 D2N
37 D2P
36 D3N
35 D3P
34 D4N
33 D4P
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
AVDD
51, 54, 55,
59, 62
BIASJ
57
CLKIN
2
CLKINC
3
CLKVDD
1
D[15..0]P
7, 11, 13,
15, 17, 19,
21, 23, 27,
29, 31, 33,
35, 37, 40,
42
I/O
DESCRIPTION
I ^{Analog supply voltage. (3.3V)}
O Full-scale output current bias. For 20mA full-scale output current, connect a 960 Ω resistor to GND.
Positive external clock input with a self-bias of approximately CLKVDD/2. With the clock multiplier PLL
I enabled, CLKIN provides lower frequency reference clock. If the PLL is disabled, CLKIN directly provides
clock for DAC up to 1GHz.
I Complementary external clock input. (See the CLKIN description)
I Internal clock buffer supply voltage. (1.8 V)
LVDS positive input data bits 0 through 15. Each positive/negative LVDS pair has an internal 100 Ω
termination resistor. Order of bus can be reversed via rev_bus bit in CONFIG5 register. Data format relative
to DCLKP/N clock is Double Data Rate (DDR) with two data samples input per DCLKP/N clock. In
I _{dual-channel mode, data for the A-channel is input while DCLKP is high.}
D15P is most significant data bit (MSB) – pin 7
D0P is least significant data bit (LSB) – pin 42
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): DAC5682Z
Submit Documentation Feedback
3