TC277 Datasheet, PDF (4/19 Pages) Texas Instruments – 735- × 580-PIXEL CCD IMAGE SENSOR

TC277
735- × 580-PIXEL CCD IMAGE SENSOR
SOCS020B – DECEMBER 1991
detailed description
The TC277 consists of four basic functional blocks: (1) the image-sensing area, (2) the image-storage area,
(3) the multiplexer with serial registers and transfer gates, and (4) the low-noise signal-processing amplifier with
charge-detection nodes. Location of each of these blocks is shown in the functional block diagram.
image-sensing and image-storage areas
Cross sections with potential-well diagrams and top views of image-sensing and storage-area elements are
shown in Figure 1 and Figure 2. As light enters the silicon in the image-sensing area, free electrons are
generated and collected in the potential wells of the sensing elements. During this time, the antiblooming gate
is activated by the application of a burst of pulses every horizontal-blanking interval. This prevents blooming
caused by the spilling of charge from overexposed elements into neighboring elements. After the completion
of integration, the signal charge is transferred into the storage area.
Thirty-three full columns and one half-column of elements at the right edge of the image-sensing area are
shielded from incident light; the 33 full columns of elements provide the dark reference used in subsequent
video-processing circuits to restore the video-black level. There are also one full column and one half-column
of light-shielded elements at the left edge of the image-sensing area and two lines of light-shielded elements
between the image-sensing and image-storage areas. The latter prevent charge leakage from the
image-sensing area into the image-storage area.
multiplexer with transfer gates and serial registers
The multiplexer and transfer gates transfers the charge line-by-line from each group of columns into the
corresponding serial register and prepares it for readout. Multiplexing is activated during the horizontal-blanking
interval by applying appropriate pulses to the transfer gates and serial registers. The required pulse timing is
shown in Figure 3. A drain is included in this area to provide the capability to quickly clear the image-sensing
and storage areas of unwanted charge. Such charge can accumulate in the imager during the start-up of
operation or under special circumstances when nonstandard TV operation is desired.
correlated-clamp sample-and-hold amplifier with charge-detection nodes
Figure 4 illustrates the correlated-clamp sample-and-hold amplifier circuit. Charge is converted into a video
signal by transferring the charge onto a floating-diffusion structure in detection node 1 that is connected to the
gate of MOS transistor Q1. The proportional charge-induced signal is then processed by the circuit shown in
Figure 4. This circuit consists of a low-pass filter formed by Q1 and C2, coupling-capacitor C1, dummy-detection
node 2, which restores the dc bias on the gate of Q3, sampling-transistor Q5, holding capacitor C3, and
output-buffer Q6. Transistors Q2, Q4, and Q7 are current sources for each corresponding stage of the amplifier.
The parameters of this high-performance signal-processing amplifier have been optimized to minimize noise
and maximize the video signal.
The signal processing begins with a reset of detection node 1 and restoration of the dc bias on the gate of Q3
through the clamping function of dummy-detection node 2. After the clamping is completed, the new charge
packet is transferred onto detection node 1. The resulting signal is sampled by the sampling-transistor Q5 and
is stored on the holding-capacitor C3. This process is repeated periodically and is correlated to the charge
transfer in the registers. The correlation is achieved automatically since the same clock lines used in registers
φ-S2 and φ-S3 for charge transport serve for reset and sample. The multiple use of the clock lines significantly
reduces the number of signals required to operate the sensor. The amplifier also contains an internal
voltage-reference generator that provides the reference bias for the reset and clamp transistors. Since the
detection nodes and the corresponding amplifiers are located some distance from the edge of the storage area,
eleven dummy elements are used at the end of each serial register to span the distance. The location of the
dummy elements, which are considered to be part of the amplifiers, is shown on the functional block diagram.
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