TC213 Datasheet, PDF (4/21 Pages) Texas Instruments – 1024- × 512-pixel ccd image sensor

TC213
1024- × 512-PIXEL CCD IMAGE SENSOR
SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991
detailed description
The TC213 consists of four basic functional blocks: (1) the image-sensing area, (2) the image-storage area,
(3) the multiplexer block with serial registers and transfer gates, and (4) the low-noise signal-processing
amplifier block with charge-detection nodes. The location of each of these blocks is identified in the functional
block diagram.
image-sensing and image-storage areas
Figures 1 and 2 show cross sections with potential well diagrams and top views of image-sensing elements. As
light enters the silicon in the image-sensing area, free electrons are generated and collected in the potential
wells of the sensing elements. During this time, blooming protection is activated by applying a burst of pulses
to the antiblooming gate inputs every horizontal blanking interval. This prevents blooming caused by the spilling
of charge from overexposed elements into neighboring elements. After integration is complete, the signal
charge is transferred into the storage area (see Figure 5).
There are 24 full columns of elements at the left edge of the image-sensing area that are shielded from incident
light; these elements provide the dark reference used in subsequent video-processing circuits to restore the
video black level. There are also two dark lines at the bottom of the image-sensing area that prevent charge
leakage from the image-sensing area into the image-storage area.
multiplexer with transfer gates and serial registers
The multiplexer and transfer gates transfer charge line by line from the image-storage area columns into the
corresponding serial registers and prepare it for readout. Figure 3 illustrates the layout of the multiplexing gate
that vertically separates the pixels for input into the serial registers. Figure 4 shows the layout of the interface
region between the serial-register gates and the transfer gates. Multiplexing is activated during the horizontal
blanking interval by applying appropriate pulses to the transfer gates and serial registers; the required pulse
timing is shown in Figure 6. A drain is also included to provide the capability to clear the image-sensing area
of unwanted charge. Such charge can accumulate in the imager during the start-up of operation or under special
circumstances when nonstandard timing is desired. The clear timing is given as part of the parallel-transfer
timing in Figure 5.
serial-register readout and video processing
After transfer into the serial registers, the pixels are normally read out 180° out of phase (see Figure 7). Each
serial register must be reset to the reference level before the next pixel is read out. The timing for the resets and
their relationships to the serial-register pulses is shown in Figure 8. Figure 8 also shows the timing for the pixel
clamp and sample and hold needed for an off-chip double-correlated sampling circuit. These two output signals
can provide a data rate of 20 million pixels per second when combined off chip. After the charge is placed on
the detection node, it is buffered and amplified by a low-noise, dual-stage source follower. Each serial register
contains 12 dummy elements that are used to span the distance between the serial register and the output
amplifier. A schematic is shown in Figure 9. The location of the dummy elements, which are considered to be
part of the amplifiers, is shown in the functional block diagram. Figure 10 gives the timing for a single frame of
video. An output of 30 frames per second with one field per frame is typical.
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