LP2989LV_15 Datasheet, PDF (4/26 Pages) Texas Instruments – Micropower and Low-Noise, 500-mA Ultra Low-Dropout Regulator for Use With Ceramic Output Capacitors

LP2989LV
SNVS086K – MAY 2000 – REVISED JULY 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
If Military/Aerospace specified devices are required contact the Texas Instruments Sales Office/Distributors for availability and
specifications. ⁽¹⁾
MIN
MAX
UNIT
Operating junction temperature
Power dissipation⁽²⁾
–40
125
°C
Internally limited
Input supply voltage, survival
–0.3
16
V
SENSE pin
Output voltage, survival⁽³⁾
–0.3
6
V
–0.3
16
V
I_OUT, Survival
Input-output voltage, survival⁽⁴⁾
Short-circuit protected
–0.3
16
V
Storage temperature range, T_stg
–65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The maximum allowable power dissipation is a function of the maximum junction temperature, T_J(MAX), the junction-to-ambient thermal
resistance, R_θJA, and the ambient temperature, T_A. The maximum allowable power dissipation at any ambient temperature is calculated
using: P_(MAX) = (T_J(MAX) – T_A) / R_θJA. The value R_θJA for the WSON (NGN) package is specifically dependent on PCB trace area, trace
material, and the number of layers and thermal vias. For improved thermal resistance and power dissipation for the WSON package,
refer to Application Note AN-1187 Leadless Leadframe Package (LLP) (SNOA401). Exceeding the maximum allowable power
dissipation causes excessive die temperature, and the regulator goes into thermal shutdown.
(3) If used in a dual-supply system where the regulator load is returned to a negative supply, the LP2989LV output must be diode-clamped
to ground.
(4) The output PNP structure contains a diode between the IN and OUT pins that is normally reverse-biased. Forcing the output above the
input turns on this diode and may induce a latch-up mode which can damage the part.
6.2 ESD Ratings
V_(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾
VALUE
±2000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
UNIT
V
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Operating junction temperature
Operating input supply voltage
MIN
MAX
UNIT
–40
125
°C
2.1
16
V
6.4 Thermal Information
THERMAL METRIC⁽¹⁾
LP2989LV
NGN (WSON)
D (SOIC)
UNIT
8 PINS
8 PINS
R_θJA
R_θJC(top)
R_θJB
ψ_JT
ψ_JB
R_θJC(bot)
Junction-to-ambient thermal resistance, High-K
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
34.8
114.5
°C/W
28.4
61.1
°C/W
12.0
55.6
°C/W
0.2
9.7
°C/W
12.2
54.9
°C/W
1.3
n/a
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
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