LP2989LV_15 Datasheet, PDF (3/26 Pages) Texas Instruments – Micropower and Low-Noise, 500-mA Ultra Low-Dropout Regulator for Use With Ceramic Output Capacitors

www.ti.com
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
LP2989LV
SNVS086K – MAY 2000 – REVISED JULY 2015
NGN Package
8-Lead WSON
Top View
NAME
BYPASS
ERROR
GROUND
INPUT
PIN
NUMBER
1
7
3
4
N/C
2
OUTPUT
5
SENSE
6
SHUTDOWN
8
Thermal Pad
—
Pin Functions
I/O
DESCRIPTION
I
Bypass capacitor input
O
Error signal output
—
GND
I
Regulator power input
DO NOT CONNECT. Device pin 2 is reserved for post packaging test and calibration
of the LP2989LV V_OUT accuracy. Device pin 2 must be left floating. Do not connect to
any potential. Do not connect to ground. Any attempt to do pin continuity testing on
—
device pin 2 is discouraged. Continuity test results are variable depending on the
actions of the factory calibration. Aggressive pin continuity testing (high voltage, or
high current) on device pin 2 may activate the trim circuitry forcing V_OUT to move out
of tolerance.
O
Regulated output voltage
I
Feedback voltage sense input
I
Shutdown input
The exposed thermal pad on the bottom of the WSON package must be connected to
a copper thermal pad on the PCB under the package. The use of thermal vias to
remove heat from the package into the PCB is recommended. Connect the thermal
—
pad to ground potential or leave floating. Do not connect the thermal pad to any
potential other than the same ground potential seen at device pin 3. For additional
information on using TI's Non Pull Back WSON package, see Application Note AN-
1187 Leadless Leadframe Package (LLP) (SNOA401).
Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: LP2989LV
Submit Documentation Feedback
3