CD54HC195_08 Datasheet, PDF (4/16 Pages) Texas Instruments – High-Speed CMOS Logic 4-Bit Parallel Access Register

CD54HC195, CD74HC195
Prerequisite For Switching Function
PARAMETER
Clock Frequency
MR Pulse Width
Clock Pulse Width
Set-up Time
J, K, PE to Clock
Hold Time
J, K, PE to Clock
Removal Time,
MR to Clock
SYMBOL
f_MAX
t_w
t_w
t_SU
t_H
t_REM
TEST
CONDITIONS V_CC (V)
-
2
4.5
6
-
2
4.5
6
-
2
4.5
6
-
2
4.5
6
-
2
4.5
6
-
2
4.5
6
25^oC
MIN MAX
6
-
30
-
35
-
80
-
16
-
14
-
80
-
16
-
14
-
100
-
20
-
17
-
3
-
3
-
5
-
80
-
16
-
14
-
-40^oC TO 85^oC -55^oC TO 125^oC
MIN MAX MIN MAX UNITS
5
-
4
-
MHz
25
-
20
-
MHz
29
-
23
-
MHz
100
-
120
-
ns
20
-
24
-
ns
17
-
20
-
ns
100
-
120
-
ns
20
-
24
-
ns
17
-
20
-
ns
125
-
150
-
ns
25
-
30
-
ns
21
-
26
-
ns
3
-
3
-
ns
3
-
3
-
ns
3
-
3
-
ns
100
-
120
-
ns
20
-
24
-
ns
17
-
20
-
ns
Switching Specifications Input t_r, t_f = 6ns
PARAMETER
HC TYPES
Propagation Delay, CP to
Output
TEST
SYMBOL CONDITIONS V_CC (V)
t_PLH, t_PHL C_L = 50pF
2
4.5
25^oC
TYP MAX
-40^oC TO 85^oC -55^oC TO 125^oC
MAX
MAX
UNITS
-
175
220
-
35
44
265
ns
53
ns
6
-
30
37
45
ns
Propagation Delay,
MR toOutput
t_PLH, t_PHL C_L = 50pF
2
-
150
190
4.5
-
30
38
225
ns
45
ns
6
-
26
33
38
ns
Output Transition Times
t_TLH, t_THL C_L = 50pF
2
-
75
95
(Figure 1)
4.5
-
15
19
110
ns
22
ns
6
-
13
16
19
ns
Input Capacitance
C_IN
-
-
-
10
10
CP to Q_n Propagation Delay t_PLH, t_PHL C_L = 15pF
5
14
-
-
MR to Q_n
t_PHL
C_L = 15pF
5
13
-
-
Maximum Clock Frequency
f_MAX
C_L = 15pF
5
50
-
-
Power Dissipation
Capacitance (Notes 2, 3)
C_PD
C_L = 15pF
45
-
-
10
pF
-
ns
-
ns
-
MHz
-
pF
NOTES:
2. C_PD is used to determine the dynamic power consumption, per flip-flop.
3. P_D = V_CC2 f_i + ∑ (C_L V_CC2 + f_O) where f_i = Input Frequency, f_O = Output Frequency, C_L = Output Load Capacitance, V_CC = Supply Voltage.
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