CD54HC195_08 Datasheet, PDF (1/16 Pages) Texas Instruments – High-Speed CMOS Logic 4-Bit Parallel Access Register

Data sheet acquired from Harris Semiconductor
SCHS165E
September 1997 - Revised October 2003
CD54HC195, CD74HC195
High-Speed CMOS Logic
4-Bit Parallel Access Register
[ /Title
(CD74
HC195
)
/Sub-
ject
(High
Speed
CMOS
Logic
4-Bit
Paral-
lel
Access
Regis-
ter)
/Autho
Features
Description
• Asynchronous Master Reset
• J, K, (D) Inputs to First Stage
• Fully Synchronous Serial or Parallel Data Transfer
• Shift Right and Parallel Load Capability
• Complementary Output From Last Stage
• Buffered Inputs
• _CTyLp=ic1a5l _pfMF,ATXA==5205M_oHCz at V_CC = 5V,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30%of V_CC at
V_CC = 5V
PInout
CD54HC195
(CERDIP)
CD74HC195
(PDIP, SOIC, SOP, TSSOP)
TOP VIEW
MR 1
J2
K3
D0 4
D1 5
D2 6
D3 7
GND 8
16 V_CC
15 Q₀
14 Q₁
13 Q₂
12 Q₃
11 Q₃
10 CP
9 PE
The device is useful in a wide variety of shifting, counting
and storage applications. It performs serial, parallel, serial to
parallel, or parallel to serial data transfers at very high
speeds.
The two modes of operation, shift right (Q₀-Q₁) and parallel
load, are controlled by the state of the Parallel Enable (PE)
input. Serial data enters the first flip-flop (Q₀) via the J and K
inputs when the PE input is high, and is shifted one bit in the
direction Q₀-Q₁-Q₂-Q₃ following each Low to High clock
transition. The J and K inputs provide the flexibility of the JK-
type input for special applications and by tying the two pins
together, the simple D-type input for general applications.
The device appears as four common-clocked D flip-flops
when the PE input is Low. After the Low to High clock
transition, data on the parallel inputs (D0-D3) is transferred
to the respective Q₀-Q₃ outputs. Shift left operation (Q₃-Q₂)
can be achieved by tying the Q_n outputs to the Dn-1 inputs
and holding the PE input low.
All parallel and serial data transfers are synchronous, occurring
after each Low to High clock transition. The ’HC195 series
utilizes edge triggering; therefore, there is no restriction on the
activity of the J, K, Pn and PE inputs for logic operations, other
than set-up and hold time requirements. A Low on the
asynchronous Master Reset (MR) input sets all Q outputs Low,
independent of any other input condition.
Ordering Information
PART NUMBER
TEMP. RANGE
(^oC)
PACKAGE
CD54HC195F3A
-55 to 125
16 Ld CERDIP
CD74HC195E
-55 to 125
16 Ld PDIP
CD74HC195M
-55 to 125
16 Ld SOIC
CD74HC195NSR
-55 to 125
16 Ld SOP
CD74HC195PW
-55 to 125
16 Ld TSSOP
CD74HC195PWR
-55 to 125
16 Ld TSSOP
CD74HC195PWT
-55 to 125
16 Ld TSSOP
NOTE: When ordering, use the entire part number. The suffix R
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1