CD54HC195_08 Datasheet, PDF(2/16 Page) Texas Instruments – High-Speed CMOS Logic 4-Bit Parallel Access Register

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

CD54HC195_08 Datasheet, PDF (2/16 Pages) Texas Instruments – High-Speed CMOS Logic 4-Bit Parallel Access Register

◁

Functional Diagram

CD54HC195, CD74HC195

PE D0 D1 D2 D3

94567

15 14 13 12

Q0 Q1 Q2 Q3

TRUTH TABLE

INPUTS

OUTPUT

OPERATING MODES MR

Asynchronous Reset

Shift, Set First Stage

Shift, Reset First Stage

Shift, Toggle First Stage

Shift, Retain First Stage

Parallel Load

H = High Voltage Level

L = Low Voltage Level,

X = Donât Care

â = Transition from Low to High Level

l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition

h = Low Voltage Level One Set-up Time prior to the High to Low Clock Transition,

dn (qn) = Lower Case Letters Indicate the State of the Referenced Input (or output) One Set-up Time Prior to the Low to High Clock

Transition.

▷