BQ24765_15 Datasheet, PDF (4/37 Pages) Texas Instruments – SMBus-Controlled Multi-Chemistry Battery Charger With Integrated Power MOSFETs

bq24765
SLUS999 – NOVEMBER 2009
www.ti.com
Table 1. Pin Functions – 34-Pin QFN (continued)
PIN
NO. NAME
FUNCTION
15 SDA
SMBus Data input. Connect to SMBus data line from the host controller. A 10-kohm pull-up resistor to the host
controller power rail is needed.
16 SCL
SMBus Clock input. Connect to SMBus clock line from the host controller. A 10-kohm pull-up resistor to the host
controller power rail is needed.
17 VDDSMB Input voltage for SMBus logic. Connect a 3.3V always supply rail, or 5V always rail to VDDSMB pin. Connect a 0.1uF
ceramic capacitor from VDDSMB to AGND for decoupling.
18 ACOK
Valid adapter active-high detect logic open-drain output. Pulled HI when Input voltage is above ACIN programmed
threshold and DCINA is above UVLO threshold. Connect a 10-kΩ pull-up resistor from ACOK pin to pull-up supply rail.
19 AGND
Analog Ground. On PCB layout, connect to the analog ground plane, and only connect to PGND through the power-pad
underneath the IC.
20 VFB
Battery voltage remote sense. Directly connect a Kelvin sense trace from the battery pack positive terminal to the VFB
pin to accurately sense the battery pack voltage. Place a 0.1-uF capacitor from VFB to AGND close to the IC to filter
high frequency noise.
21 CSON
Charge current sense resistor, negative input. An optional 0.1-uF ceramic capacitor is placed from CSON pin to AGND
for common-mode filtering. A 0.1-uF ceramic capacitor is placed from CSON to CSOP to provide differential-mode
filtering. The capacitor of the output LC filter is placed on CSON.
22 CSOP
Charge current sense resistor, positive input. A 0.1-uF ceramic capacitor is placed from CSOP pin to AGND for
common mode filtering. A 0.1-uF ceramic capacitor is placed from CSON to CSOP to provide differential-mode filtering.
23 ICOUT Low power mode detect active-high open-drain logic output. Place a 10kohm pull-up resistor from ICOUT pin to the
pull-up voltage rail. Place a positive feedback resistor from ICOUT pin to ICREF pin for programming hysteresis. The
output is HI when VICM pin voltage is lower than ICREF pin voltage. The output is LO when VICM pin voltage is higher
than ICREF pin voltage.
24 VDDP
PWM low side driver positive 6V supply output. Connect a 1uF ceramic capacitor from VDDP to PGND pin, close to the
IC. Use for high-side driver bootstrap voltage by connecting a small signal Schottky diode from VDDP to BOOT.
25 DCINA Analog sense of IC power positive supply for internal reference bias circuit. Connect directly to adapter input, or to
diode-OR point of adapter and battery. Place a 20Ω and 0.5uF ceramic capacitor filter from adapter to AGND pin close
to the IC and connect to DCINA on the node between the resistor and capacitor.
26 BOOT
PWM high side driver positive supply. Connect a 0.1uF bootstrap ceramic capacitor from BOOT to PHASE. Connect a
small bootstrap Schottky diode from VDDP to BOOT.
27 PHASE Phase switching node (junction of the integrated high-side power MOSFET source and the integrated low-side power
MOSFET drain). Connect to the output inductor. Connect the 0.1uF bootstrap ceramic capacitor from PHASE to BOOT.
28 PHASE Phase switching node (junction of the integrated high-side power MOSFET source and the integrated low-side power
MOSFET drain). Connect to the output inductor. Connect the 0.1uF bootstrap ceramic capacitor from PHASE to BOOT
29 PHASE Phase switching node (junction of the integrated high-side power MOSFET source and the integrated low-side power
MOSFET drain). Connect to the output inductor. Connect the 0.1uF bootstrap ceramic capacitor from PHASE to BOOT
30 PHASE Phase switching node (junction of the integrated high-side power MOSFET source and the integrated low-side power
MOSFET drain). Connect to the output inductor. Connect the 0.1uF bootstrap ceramic capacitor from PHASE to BOOT.
31 PHASE Phase switching node (junction of the integrated high-side power MOSFET source and the integrated low-side power
MOSFET drain). Connect to the output inductor. Connect the 0.1uF bootstrap ceramic capacitor from PHASE to BOOT.
32 PGND
Power ground. Connection to source of integrated low-side power MOSFET. On PCB layout, connect to ground
connection of in put and out put capacitors of the charger. Only connect to AGND through the power-pad underneath
the IC.
33 PGND
Power ground. Connection to source of integrated low-side power MOSFET. On PCB layout, connect to ground
connection of in put and out put capacitors of the charger. Only connect to AGND through the power-pad underneath
the IC
34 PGND
Power ground. Connection to source of integrated low-side power MOSFET. On PCB layout, connect to ground
connection of in put and out put capacitors of the charger. Only connect to AGND through the power-pad underneath
the IC.
Power
Pad
Exposed pad beneath the IC. AGND and PGND star-connected only at the Power Pad plane. Always solder Power Pad
to the board, and have vias on the Power Pad plane connecting to AGND and PGND planes. It also serves as a
thermal pad to dissipate heat.
4
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