BQ24765_15 Datasheet, PDF (18/37 Pages) Texas Instruments – SMBus-Controlled Multi-Chemistry Battery Charger With Integrated Power MOSFETs

bq24765
SLUS999 – NOVEMBER 2009
DETAILED DESCRIPTION
www.ti.com
SMBus INTERFACE
The bq24765 operates as a slave, receiving control inputs from the embedded controller host through the SMBus
interface.
BATTERY-CHARGER COMMANDS
The bq24765 supports five battery-charger commands that use either Write-Word or Read-Word protocols, as
summarized in Table 2. ManufacturerID() and DeviceID() can be used to identify the bq24765. On the bq24765,
the ManufacturerID() command always returns 0x0040 and the DeviceID() command always returns 0x0006.
REGISTER
ADDRESS
0x14
0x15
0x3F
0xFE
0xFF
Table 2. Battery Charger SMBus Registers
REGISTER NAME READ/WRITE
DESCRIPTION
ChargeCurrent()
ChargeVoltage()
InputCurrent()
ManufacturerID()
DeviceID()
Read or Write
Read or Write
Read or Write
Read Only
Read Only
6-Bit Charge Current Setting
11-Bit Charge Voltage Setting
6-Bit Input Current Setting
Manufacturer ID
Device ID
POR
STATE
0x0000
0x0000
0x0080
0x0040
0x0007
POR
VOLTAGE/CURRENT
0mA
0mV
256mA (10mΩ RAC)
–
–
SMBus Interface
The bq24765 receives control inputs from the SMBus interface. The bq24765 uses a simplified subset of the
commands documented in System Management Bus Specification V1.1, which can be downloaded from
www.smbus.org. The bq24765 uses the SMBus Read-Word and Write-Word protocols (see Figure 28) to
communicate with the smart battery. The bq24765 performs only as an SMBus slave device with address
0b0001001_ (0x12) and does not initiate communication on the bus. In addition, the bq24765 has two
identification (ID) registers (0xFE): a 16-bit device ID register and a 16-bit manufacturer ID register (0xFF).
The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose
pullup resistors (10kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications.
Communication starts when the master signals a START condition, which is a high-to-low transition on SDA,
while SCL is high. When the master has finished communicating, the master issues a STOP condition, which is a
low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 29 and
Figure 30 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and
data bytes are transmitted between the START and STOP conditions. The SDA state changes only while SCL is
low, except for the START and STOP conditions. Data is transmitted in 8-bit bytes and is sampled on the rising
edge of SCL. Nine clock cycles are required to transfer each byte in or out of the bq24765 because either the
master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle.
18
Submit Documentation Feedback
Product Folder Link(s) :bq24765
Copyright © 2009, Texas Instruments Incorporated